 | 2012 |
|---|
| 10 |       | Vinayak Honkote,
Ankit More,
Baris Taskin:
3-D Parasitic Modeling for Rotary Interconnects.
VLSI Design 2012: 137-142 |
| 2011 |
|---|
| 9 | | Jianchao Lu,
Vinayak Honkote,
Xin Chen,
Baris Taskin:
Steiner tree based rotary clock routing with bounded skew and capacitive load balancing.
DATE 2011: 455-460 |
| 8 | | Vinayak Honkote,
Baris Taskin:
CROA: Design and Analysis of the Custom Rotary Oscillatory Array.
IEEE Trans. VLSI Syst. 19(10): 1837-1847 (2011) |
| 2010 |
|---|
| 7 | | Vinayak Honkote,
Baris Taskin:
Skew-aware capacitive load balancing for low-power zero clock skew rotary oscillatory array.
ICCD 2010: 209-214 |
| 6 | | Vinayak Honkote,
Baris Taskin:
PEEC based parasitic modeling for power analysis on custom rotary rings.
ISLPED 2010: 111-116 |
| 5 | | Vinayak Honkote,
Baris Taskin:
Skew analysis and bounded skew constraint methodology for rotary clocking technology.
ISQED 2010: 413-417 |
| 4 | | Vinayak Honkote:
Design Automation and Analysis of Resonant Rotary Clocking Technology.
ISVLSI 2010: 471-472 |
| 3 | | Vinayak Honkote,
Baris Taskin:
Analysis, Design and Simulation of Capacitive Load Balanced Rotary Oscillatory Array.
VLSI Design 2010: 218-223 |
| 2009 |
|---|
| 2 | | Vinayak Honkote,
Baris Taskin:
Zero clock skew synchronization with rotary clocking technology.
ISQED 2009: 588-593 |
| 2008 |
|---|
| 1 | | Vinayak Honkote,
Baris Taskin:
Custom rotary clock router.
ICCD 2008: 114-119 |
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