 | 2012 |
|---|
| 11 |       | Hao-Chiao Hong:
A Static Linear Behavior Analog Fault Model for Switched-Capacitor Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 31(4): 597-609 (2012) |
| 2011 |
|---|
| 10 | | Sheng-Chuan Liang,
Hao-Chiao Hong:
A Digitally Testable Sigma -Delta Modulator Using the Decorrelating Design-for-Digital-Testability.
IEEE Trans. VLSI Syst. 19(3): 503-507 (2011) |
| 2010 |
|---|
| 9 | | Hao-Chiao Hong,
Fang-Yi Su,
Shao-Feng Hung:
A Fully Integrated Built-In Self-Test Sigma-Delta ADC Based on the Modified Controlled Sine-Wave Fitting Procedure.
IEEE T. Instrumentation and Measurement 59(9): 2334-2344 (2010) |
| 2009 |
|---|
| 8 | | Shao-Feng Hung,
Hao-Chiao Hong,
Sheng-Chuan Liang:
A Low-Cost Output Response Analyzer for the Built-in-Self-Test S-? Modulator Based on the Controlled Sine Wave Fitting Method.
Asian Test Symposium 2009: 385-388 |
| 7 | | Hao-Chiao Hong,
Sheng-Chuan Liang:
A Decorrelating Design-for-Digital-Testability Scheme for Sigma-Delta Modulators.
IEEE Trans. on Circuits and Systems 56-I(1): 60-73 (2009) |
| 6 | | Hao-Chiao Hong,
Sheng-Chuan Liang,
Hong-Chin Song:
A Built-in-Self-Test Sigma-Delta ADC Prototype.
J. Electronic Testing 25(2-3): 145-156 (2009) |
| 2008 |
|---|
| 5 | | Hao-Chiao Hong,
Sheng-Chuan Liang,
Hong-Chin Song:
A Cost Effective BIST Second-Order Sigma-Delta-Modulator.
DDECS 2008: 314-319 |
| 2007 |
|---|
| 4 | | Hao-Chiao Hong:
A Design-for-Digital-Testability Circuit Structure for Sigma-Delta Modulators.
IEEE Trans. VLSI Syst. 15(12): 1341-1350 (2007) |
| 3 | | Hao-Chiao Hong:
A Fully-Settled Linear Behavior Plus Noise Model for Evaluating the Digital Stimuli of the Design-for-Digital-Testability Sigma-Delta Modulators.
J. Electronic Testing 23(6): 527-538 (2007) |
| 2004 |
|---|
| 2 | | Hao-Chiao Hong,
Cheng-Wen Wu,
Kwang-Ting Cheng:
A Signa-Delta Modulation Based Analog BIST System with a Wide Bandwidth Fifth-Order Analog Response Extractor for Diagnosis Purpose.
Asian Test Symposium 2004: 62-67 |
| 2002 |
|---|
| 1 | | Hao-Chiao Hong,
Jiun-Lang Huang,
Kwang-Ting Cheng,
Cheng-Wen Wu:
On-chip Analog Response Extraction with 1-Bit ? - Modulators.
Asian Test Symposium 2002: 49- |
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