Katsumi Homma

	2012
6		Tsutomu Ishida, Izumi Nitta, Katsumi Homma, Yuzi Kanazawa, Hiroaki Komatsu: Speed-path analysis for multi-path failed latches with random variation. ISQED 2012: 545-552
	2010
5		Yu Liu, Masato Yoshioka, Katsumi Homma, Toshiyuki Shibuya, Yuzi Kanazawa: Generation of yield-embedded Pareto-front for simultaneous optimization of yield and performances. DAC 2010: 909-912
	2009
4		Yu Liu, Masato Yoshioka, Katsumi Homma, Toshiyuki Shibuya: Efficiently finding the 'best' solution with multi-objectives from multiple topologies in topology library of analog circuit. ASP-DAC 2009: 498-503
3		Yu Liu, Masato Yoshioka, Katsumi Homma, Toshiyuki Shibuya: Find the 'Best' Solution from Multiple Analog Topologies via Pareto-Optimality. IEICE Transactions 92-A(12): 3035-3043 (2009)
	2008
2		Katsumi Homma, Izumi Nitta, Toshiyuki Shibuya: Non-Gaussian Statistical Timing models of die-to-die and within-die parameter variations for full chip analysis. ASP-DAC 2008: 292-297
	1998
1		Hisakazu Edamatsu, Katsumi Homma, Masaru Kakimoto, Yutaka Koike, Kinya Tabuchi: Pre-layout Delay Calculation Specification for CMOS ASIC Libraries. ASP-DAC 1998: 241-248

Coauthor Index

1	Hisakazu Edamatsu	[1]
2	Tsutomu Ishida	[6]
3	Masaru Kakimoto	[1]
4	Yuzi Kanazawa	[5] [6]
5	Yutaka Koike	[1]
6	Hiroaki Komatsu	[6]
7	Yu Liu	[3] [4] [5]
8	Izumi Nitta	[2] [6]
9	Toshiyuki Shibuya	[2] [3] [4] [5]
10	Kinya Tabuchi	[1]
11	Masato Yoshioka	[3] [4] [5]

Colors in the list of coauthors

Last update Sat Jun 2 20:57:36 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page