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Ronald Ho
List of publications from the DBLP Bibliography Server - FAQ
| 2011 | ||
|---|---|---|
| 17 | Tamer A. Ali, Amr Amin Hafez, Robert J. Drost, Ronald Ho, Chih-Kong Ken Yang: A 4.6GHz MDLL with -46dBc reference spur and aperture position tuning. ISSCC 2011: 466-468 | |
| 2010 | ||
| 16 | Ron Ho, John E. Cunningham, Herb Schwetman, Xuezhe Zheng, Ashok V. Krishnamoorthy: Optical Interconnects in the Data Center. Hot Interconnects 2010: 117-120 | |
| 15 | Tamer A. Ali, Dinesh Patil, Frankie Liu, Elad Alon, Jon Lexau, Chih-Kong Ken Yang, Ron Ho: Clocking Links in Multi-chip Packages: A Case Study. Hot Interconnects 2010: 96-103 | |
| 14 | Pranay Koka, Michael O. McCracken, Herb Schwetman, Xuezhe Zheng, Ron Ho, Ashok V. Krishnamoorthy: Silicon-photonic network architectures for scalable, power-efficient multi-chip systems. ISCA 2010: 117-128 | |
| 13 | Jae-sun Seo, Ron Ho, Jon Lexau, Michael Dayringer, Dennis Sylvester, David Blaauw: High-bandwidth and low-energy on-chip signaling with adaptive pre-emphasis in 90nm CMOS. ISSCC 2010: 182-183 | |
| 12 | Ron Ho, Frankie Liu, Dinesh Patil, Xuezhe Zheng, Guoliang Li, Ivan Shubin, Elad Alon, Jon Lexau, Herb Schwetman, John E. Cunningham, Ashok V. Krishnamoorthy: Optical Interconnect for High-End Computer Systems. IEEE Design & Test of Computers 27(4): 10-19 (2010) | |
| 11 | Vladimir Stojanovic, Chih-Kong Ken Yang, Ron Ho: Guest Editorial for Special Issue on High-Performance Multichip Interconnections. IEEE Trans. on Circuits and Systems 57-II(5): 317-318 (2010) | |
| 2008 | ||
| 10 | Ashok V. Krishnamoorthy, Jon Lexau, Xuezhe Zheng, John E. Cunningham, Ron Ho, Ola Tørudbakken: Optical Interconnects for Present and Future High-Performance Computing Systems. Hot Interconnects 2008: 175-177 | |
| 2007 | ||
| 9 | Frankie Liu, Ron Ho, Robert J. Drost, Scott Fairbanks: On-chip samplers for test and debug of asynchronous circuits. ASYNC 2007: 153-162 | |
| 8 | Dinesh Patil, Omid Azizi, Mark Horowitz, Ron Ho, Rajesh Ananthraman: Robust Energy-Efficient Adder Topologies. IEEE Symposium on Computer Arithmetic 2007: 16-28 | |
| 7 | John D. Owens, William J. Dally, Ron Ho, D. N. Jayasimha, Stephen W. Keckler, Li-Shiuan Peh: Research Challenges for On-Chip Interconnection Networks. IEEE Micro 27(5): 96-108 (2007) | |
| 2005 | ||
| 6 | Robert J. Drost, Craig Forrest, Bruce Guenin, Ron Ho, Ashok V. Krishnamoorthy, Danny Cohen, John E. Cunningham, Bernard Tourancheau, Arthur Zingher, Alex Chow, Gary Lauterbach, Ivan E. Sutherland: Challenges in Building a Flat-Bandwidth Memory Hierarchy for a Large-Scale Computer with Proximity Communication. Hot Interconnects 2005: 13-22 | |
| 5 | Ron Ho: High-performance ULSI: the real limiter to interconnect scaling. SLIP 2005: 3 | |
| 2004 | ||
| 4 | Ron Ho, Jonathan Gainsley, Robert J. Drost: Long Wires and Asynchronous Control. ASYNC 2004: 240-249 | |
| 3 | Yun Zhang, Mihai Burcea, Victor Cheng, Ron Ho, Michael Voss: An Adaptive OpenMP Loop Scheduler for Hyperthreaded SMPs. ISCA PDCS 2004: 256-263 | |
| 2000 | ||
| 2 | Ken Mai, Tim Paaske, Nuwan Jayasena, Ron Ho, William J. Dally, Mark Horowitz: Smart Memories: a modular reconfigurable architecture. ISCA 2000: 161-171 | |
| 1999 | ||
| 1 | Ron Ho, Ken Mai, Hema Kapadia, Mark Horowitz: Interconnect scaling implications for CAD. ICCAD 1999: 425-429 | |
Colors in the list of coauthors
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