 | 2012 |
|---|
| 7 |       | Kuan-Hsien Ho,
Xin-Wei Shih,
Jie-Hong R. Jiang:
Clock rescheduling for timing engineering change orders.
ASP-DAC 2012: 517-522 |
| 2010 |
|---|
| 6 | | Kuan-Hsien Ho,
Jie-Hong R. Jiang,
Yao-Wen Chang:
TRECO: dynamic technology remapping for timing engineering change orders.
ASP-DAC 2010: 331-336 |
| 5 | | Xin-Wei Shih,
Hsu-Chieh Lee,
Kuan-Hsien Ho,
Yao-Wen Chang:
High variation-tolerant obstacle-avoiding clock mesh synthesis with symmetrical driving trees.
ICCAD 2010: 452-457 |
| 4 | | Kuan-Hsien Ho,
Yen-Pin Chen,
Jia-Wei Fang,
Yao-Wen Chang:
ECO Timing Optimization Using Spare Cells and Technology Remapping.
IEEE Trans. on CAD of Integrated Circuits and Systems 29(5): 697-710 (2010) |
| 2009 |
|---|
| 3 | | Po-Yuan Chen,
Kuan-Hsien Ho,
TingTing Hwang:
Skew-aware polarity assignment in clock tree.
ACM Trans. Design Autom. Electr. Syst. 14(2): (2009) |
| 2008 |
|---|
| 2 | | Jia-Wei Fang,
Kuan-Hsien Ho,
Yao-Wen Chang:
Routing for chip-package-board co-design considering differential pairs.
ICCAD 2008: 512-517 |
| 2007 |
|---|
| 1 | | Po-Yuan Chen,
Kuan-Hsien Ho,
TingTing Hwang:
Skew aware polarity assignment in clock tree.
ICCAD 2007: 376-379 |
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