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Tetsuo Hironaka Coauthor index pubzone.org

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DBLP keys2012
16Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLMasatoshi Nakamura, Masato Inagi, Kazuya Tanigawa, Tetsuo Hironaka, Masayuki Sato, Takashi Ishiguro: A Physical Design Method for a New Memory-Based Reconfigurable Architecture without Switch Blocks. IEICE Transactions 95-D(2): 324-334 (2012)
2011
15Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLMasatoshi Nakamura, Masato Inagi, Kazuya Tanigawa, Tetsuo Hironaka, Masayuki Sato, Takashi Ishiguro: EDA Environment for Evaluating a New Switch-Block-Free Reconfigurable Architecture. ReConFig 2011: 448-454
2010
14Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLKazuya Tanigawa, Ken'ichi Umeda, Tetsuo Hironaka: Comparison of Bit Serial Computation with Bit Parallel Computation for Reconfigurable Processor. ARC 2010: 388-393
2008
13Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLKazuya Tanigawa, Tetsuya Zuyama, Takuro Uchida, Tetsuo Hironaka: Exploring compact design on high throughput coarse grained reconfigurable architectures. FPL 2008: 543-546
12Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLTakahiro Sasaki, Yuji Ichikawa, Tetsuo Hironaka, Toshiaki Kitamura, Toshio Kondo: Evaluation of low-energy and high-performance processor using variable stages pipeline technique. IET Computers & Digital Techniques 2(3): 230-238 (2008)
2007
11Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLKoh Johguchi, Hans Jürgen Mattausch, Tetsushi Koide, Tetsuo Hironaka: 4-Port Unified Data/Instruction Cache Design with Distributed Crossbar and Interleaved Cache-Line Words. IEICE Transactions 90-C(11): 2157-2160 (2007)
2006
10Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLKoh Johguchi, Zhaomin Zhu, Hans Jürgen Mattausch, Tetsushi Koide, Tetsuo Hironaka, Kazuya Tanigawa: Unified Data/Instruction Cache with Hierarchical Multi-Port Architecture and Hidden Precharge Pipeline. APCCAS 2006: 1297-1300
9Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLTakahiro Sasaki, Tetsuo Hironaka, Naoki Nishimura, Noriyoshi Yoshida: Scheduling support hardware for multiprocessor system and its evaluations. Systems and Computers in Japan 37(2): 79-95 (2006)
2005
8Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLT. Saito, M. Maeda, Tetsuo Hironaka, Kazuya Tanigawa, Tetsuya Sueyoshi, K. Aoyama, Tetsushi Koide, Hans Jürgen Mattausch: Design of superscalar processor with multi-bank register file. ISCAS (4) 2005: 3507-3510
7Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLTakahiro Sasaki, Tomohiro Inoue, Nobuhiko Omori, Tetsuo Hironaka, Hans Jürgen Mattausch, Tetsushi Koide: Chip size and performance evaluations of shared cache for on-chip multiprocessor. Systems and Computers in Japan 36(9): 1-13 (2005)
2004
6Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLTetsuya Sueyoshi, Hiroshi Uchida, Hans Jürgen Mattausch, Tetsushi Koide, Yosuke Mitani, Tetsuo Hironaka: Compact 12-port multi-bank register file test-chip in 0.35µm CMOS for highly parallel processors. ASP-DAC 2004: 551-552
2002
5Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLKazuya Tanigawa, Tetsuo Hironaka, Akira Kojima, Noriyoshi Yoshida: A Generalized Execution Model for Programming on Reconfigurable Architectures and an Architecture Supporting the Model. FPL 2002: 434-443
2000
4Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLNaoki Nishimura, Takahiro Sasaki, Tetsuo Hironaka: Prototype microprocessor LSI with scheduling support hardware for operating system on multiprocessor system. ASP-DAC 2000: 29-30
3no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLTakahiro Sasaki, Tetsuo Hironaka, Seiji Fujino: Performance Improvements of Thakore's Algorithm with Speculative Execution Technique and Dynamic Task Scheduling. Informatica (Slovenia) 24(1): (2000)
1993
2Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLTakashi Hashimoto, Kazuaki Murakami, Tetsuo Hironaka, Hiroto Yasuura: A Micro-Vectorprocessor Architecture: Performance Modeling and Benchmarking. International Conference on Supercomputing 1993: 308-317
1992
1Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLTetsuo Hironaka, Takashi Hashimoto, Keizo Okazaki, Kazuaki Murakami, Shinji Tomita: Benchmarking a vector-processor prototype based on multithreaded streaming/FIFO vector (MSFV) architecture. ICS 1992: 272-281

Coauthor Index

1K. Aoyama [8]
2Seiji Fujino [3]
3Takashi Hashimoto [1] [2]
4Yuji Ichikawa [12]
5Masato Inagi [15] [16]
6Tomohiro Inoue [7]
7Takashi Ishiguro [15] [16]
8Koh Johguchi [10] [11]
9Toshiaki Kitamura [12]
10Tetsushi Koide [6] [7] [8] [10] [11]
11Akira Kojima [5]
12Toshio Kondo [12]
13M. Maeda [8]
14Hans Jürgen Mattausch [6] [7] [8] [10] [11]
15Yosuke Mitani [6]
16Kazuaki Murakami [1] [2]
17Masatoshi Nakamura [15] [16]
18Naoki Nishimura [4] [9]
19Keizo Okazaki [1]
20Nobuhiko Omori [7]
21T. Saito [8]
22Takahiro Sasaki [3] [4] [7] [9] [12]
23Masayuki Sato [15] [16]
24Tetsuya Sueyoshi [6] [8]
25Kazuya Tanigawa [5] [8] [10] [13] [14] [15] [16]
26Shinji Tomita [1]
27Hiroshi Uchida [6]
28Takuro Uchida [13]
29Ken'ichi Umeda [14]
30Hiroto Yasuura [2]
31Noriyoshi Yoshida [5] [9]
32Zhaomin Zhu [10]
33Tetsuya Zuyama [13]

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