 | 2010 |
|---|
| 6 |       | Mokhtar Hirech:
Test cost and test power conflicts: EDA perspective.
VTS 2010: 126 |
| 2008 |
|---|
| 5 | | C. P. Ravikumar,
Mokhtar Hirech,
Xiaoqing Wen:
Test Strategies for Low Power Devices.
DATE 2008: 728-733 |
| 4 | | C. P. Ravikumar,
Mokhtar Hirech,
Xiaoqing Wen:
Test Strategies for Low-Power Devices.
J. Low Power Electronics 4(2): 127-138 (2008) |
| 2005 |
|---|
| 3 | | Aurelia De Colle,
Sanjay Ramnath,
Mokhtar Hirech,
Subramanian Chebiyam:
Power and Design for Test: A Design Automation Perspective.
J. Low Power Electronics 1(1): 73-84 (2005) |
| 2002 |
|---|
| 2 | | Sanjay Ramnath,
Frederic Neuveux,
Mokhtar Hirech,
Felix Ng:
Test-model based hierarchical DFT synthesis.
ICCAD 2002: 286-293 |
| 1998 |
|---|
| 1 | | Mokhtar Hirech,
James Beausang,
Xinli Gu:
A new approach to scan chain reordering using physical design information.
ITC 1998: 348-355 |
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