Junichi Hirase

	2005
13		Junichi Hirase, Yoshiyuki Goi, Yoshiyuki Tanaka: IDDQ Testing Method using a Scan Pattern for Production Testing. Asian Test Symposium 2005: 18-21
12		Junichi Hirase, Tatsuya Furukawa: Chip Identification using the Characteristic Dispersion of Transistor. Asian Test Symposium 2005: 188-193
	2003
11		Junichi Hirase: Test Pattern Length Required to Reach the Desired Fault Coverage. Asian Test Symposium 2003: 508
	2002
10		Junichi Hirase: High Precision Result Evaluation of VLSI. Asian Test Symposium 2002: 21-26
	2001
9		Junichi Hirase: Test Time Reduction through Minimum Execution of Tester-Hardware Setting Instructions. Asian Test Symposium 2001: 173-178
8		Junichi Hirase: Yield Increase of VLSI after Redundancy-Repairing. Asian Test Symposium 2001: 353-358
	2000
7		Junichi Hirase, Shinichi Yoshimura: Faster processing for microprocessor functional ATPG. Asian Test Symposium 2000: 191-197
	1999
6		Junichi Hirase, Shinichi Yoshimura, Tomohisa Sczaki: Automatic Test Pattern Generation for Improving the Fault Coverage of Microprocessors. Asian Test Symposium 1999: 13-19
5		Junichi Hirase, Naoki Shindou, Kouji Akahori: Scan Chain Diagnosis Using IDDQ Current Measurement. Asian Test Symposium 1999: 153-157
	1998
4		Junichi Hirase: Economical Importance of the Maximum Chip Area. Asian Test Symposium 1998: 64-
	1995
3		Junichi Hirase: Improvement of the Defect Level of Micro-computer LSI Testing. ITC 1995: 377-383
2		Junichi Hirase: Study on the Costs of On-site VLSI Testing. ITC 1995: 438-443
1		Junichi Hirase, Masanori Hamada: The Effect of CMOS VLSI IDDq Measurement on Defect Level. IEICE Transactions 78-D(7): 839-844 (1995)

Coauthor Index

1	Kouji Akahori	[5]
2	Tatsuya Furukawa	[12]
3	Yoshiyuki Goi	[13]
4	Masanori Hamada	[1]
5	Tomohisa Sczaki	[6]
6	Naoki Shindou	[5]
7	Yoshiyuki Tanaka	[13]
8	Shinichi Yoshimura	[6] [7]

Colors in the list of coauthors

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