dblp.uni-trier.dewww.dagstuhl.dewww.uni-trier.de

Osamu Hirabayashi Coauthor index pubzone.org

List of publications from the DBLP Bibliography Server - FAQ
Ask others: ACM DL/Guide - CiteSeerX - CSB - MetaPress - Google - Bing - Yahoo

DBLP keys2011
6Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLYusuke Niki, Atsushi Kawasumi, Azuma Suzuki, Yasuhisa Takeyama, Osamu Hirabayashi, Keiichi Kushida, Fumihiko Tachibana, Yuki Fujimura, Tomoaki Yabe: A Digitized Replica Bitline Delay Technique for Random-Variation-Tolerant Timing Generation of SRAM Sense Amplifiers. J. Solid-State Circuits 46(11): 2545-2551 (2011)
2010
5Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLYuki Fujimura, Osamu Hirabayashi, Takahiko Sasaki, Azuma Suzuki, Atsushi Kawasumi, Yasuhisa Takeyama, Keiichi Kushida, Gou Fukano, Akira Katayama, Yusuke Niki, Tomoaki Yabe: A configurable SRAM with constant-negative-level write buffer for low-voltage operation with 0.149µm2 cell in 32nm high-k metal-gate CMOS. ISSCC 2010: 348-349
4Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLAtsushi Kawasumi, Yasuhisa Takeyama, Osamu Hirabayashi, Keiichi Kushida, Yuki Fujimura, Tomoaki Yabe: A Low-Supply-Voltage-Operation SRAM With HCI Trimmed Sense Amplifiers. J. Solid-State Circuits 45(11): 2341-2347 (2010)
2009
3Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLOsamu Hirabayashi, Atsushi Kawasumi, Azuma Suzuki, Yasuhisa Takeyama, Keiichi Kushida, Takahiko Sasaki, Akira Katayama, Gou Fukano, Yuki Fujimura, Takaaki Nakazato, Yasushi Shizuki, Natsuki Kushiyama, Tomoaki Yabe: A process-variation-tolerant dual-power-supply SRAM with 0.179µm2 Cell in 40nm CMOS using level-programmable wordline driver. ISSCC 2009: 458-459
2008
2Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLAkira Katayama, Tomoaki Yabe, Osamu Hirabayashi, Yasuhisa Takeyama, Keiichi Kushida, Takahiko Sasaki, Nobuaki Otsuka: Direct Cell-Stability Test Techniques for an SRAM Macro with Asymmetric Cell-Bias-Voltage Modulation. ITC 2008: 1-7
2002
1Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLOsamu Hirabayashi, Azuma Suzuki, Tomoaki Yabe, Atsushi Kawasumi, Yasuhisa Takeyama, Keiichi Kushida, A. Tohata, Nobuaki Otsuka: DFT Techniques for Wafer-Level At-Speed Testing of High-Speed SRAMs. ITC 2002: 164-169

Coauthor Index

1Yuki Fujimura [3] [4] [5] [6]
2Gou Fukano [3] [5]
3Akira Katayama [2] [3] [5]
4Atsushi Kawasumi [1] [3] [4] [5] [6]
5Keiichi Kushida [1] [2] [3] [4] [5] [6]
6Natsuki Kushiyama [3]
7Takaaki Nakazato [3]
8Yusuke Niki [5] [6]
9Nobuaki Otsuka [1] [2]
10Takahiko Sasaki [2] [3] [5]
11Yasushi Shizuki [3]
12Azuma Suzuki [1] [3] [5] [6]
13Fumihiko Tachibana [6]
14Yasuhisa Takeyama [1] [2] [3] [4] [5] [6]
15A. Tohata [1]
16Tomoaki Yabe [1] [2] [3] [4] [5] [6]

Last update Thu May 31 18:55:10 2012 CET by the DBLP TeamThis material is Open Data Data released under the ODC-BY 1.0 license — See also our legal information page