 | 2011 |
| 6 |  | Yusuke Niki,
Atsushi Kawasumi,
Azuma Suzuki,
Yasuhisa Takeyama,
Osamu Hirabayashi,
Keiichi Kushida,
Fumihiko Tachibana,
Yuki Fujimura,
Tomoaki Yabe:
A Digitized Replica Bitline Delay Technique for Random-Variation-Tolerant Timing Generation of SRAM Sense Amplifiers.
J. Solid-State Circuits 46(11): 2545-2551 (2011) |
| 2010 |
| 5 |  | Yuki Fujimura,
Osamu Hirabayashi,
Takahiko Sasaki,
Azuma Suzuki,
Atsushi Kawasumi,
Yasuhisa Takeyama,
Keiichi Kushida,
Gou Fukano,
Akira Katayama,
Yusuke Niki,
Tomoaki Yabe:
A configurable SRAM with constant-negative-level write buffer for low-voltage operation with 0.149µm2 cell in 32nm high-k metal-gate CMOS.
ISSCC 2010: 348-349 |
| 4 |  | Atsushi Kawasumi,
Yasuhisa Takeyama,
Osamu Hirabayashi,
Keiichi Kushida,
Yuki Fujimura,
Tomoaki Yabe:
A Low-Supply-Voltage-Operation SRAM With HCI Trimmed Sense Amplifiers.
J. Solid-State Circuits 45(11): 2341-2347 (2010) |
| 2009 |
| 3 |  | Osamu Hirabayashi,
Atsushi Kawasumi,
Azuma Suzuki,
Yasuhisa Takeyama,
Keiichi Kushida,
Takahiko Sasaki,
Akira Katayama,
Gou Fukano,
Yuki Fujimura,
Takaaki Nakazato,
Yasushi Shizuki,
Natsuki Kushiyama,
Tomoaki Yabe:
A process-variation-tolerant dual-power-supply SRAM with 0.179µm2 Cell in 40nm CMOS using level-programmable wordline driver.
ISSCC 2009: 458-459 |
| 2008 |
| 2 |  | Akira Katayama,
Tomoaki Yabe,
Osamu Hirabayashi,
Yasuhisa Takeyama,
Keiichi Kushida,
Takahiko Sasaki,
Nobuaki Otsuka:
Direct Cell-Stability Test Techniques for an SRAM Macro with Asymmetric Cell-Bias-Voltage Modulation.
ITC 2008: 1-7 |
| 2002 |
| 1 |  | Osamu Hirabayashi,
Azuma Suzuki,
Tomoaki Yabe,
Atsushi Kawasumi,
Yasuhisa Takeyama,
Keiichi Kushida,
A. Tohata,
Nobuaki Otsuka:
DFT Techniques for Wafer-Level At-Speed Testing of High-Speed SRAMs.
ITC 2002: 164-169 |