Andrew D. Hilton

	2012
8		Steven Battle, Andrew D. Hilton, Mark Hempstead, Amir Roth: Flexible register management using reference counting. HPCA 2012: 273-284
	2010
7		Andrew D. Hilton, Amir Roth: BOLT: Energy-efficient Out-of-Order Latency-Tolerant execution. HPCA 2010: 1-12
6		Andrew D. Hilton, Amir Roth: SMT-Directory: Efficient Load-Load Ordering for SMT. Computer Architecture Letters 9(1): 25-28 (2010)
5		Andrew D. Hilton, Santosh Nagarakatte, Amir Roth: iCFP: Tolerating All-Level Cache Misses in In-Order Processors. IEEE Micro 30(1): 12-19 (2010)
	2009
4		Andrew D. Hilton, Santosh Nagarakatte, Amir Roth: iCFP: Tolerating all-level cache misses in in-order processors. HPCA 2009: 431-442
3		Andrew D. Hilton, Amir Roth: Decoupled store completion/silent deterministic replay: enabling scalable data memory for CPR/CFP processors. ISCA 2009: 245-254
2		Andrew D. Hilton, Neeraj Eswaran, Amir Roth: CPROB: Checkpoint Processing with Opportunistic Minimal Recovery. PACT 2009: 159-168
	2007
1		Andrew D. Hilton, Amir Roth: Ginger: control independence using tag rewriting. ISCA 2007: 436-447

Coauthor Index

1	Steven Battle	[8]
2	Neeraj Eswaran	[2]
3	Mark Hempstead	[8]
4	Santosh Nagarakatte	[4] [5]
5	Amir Roth	[1] [2] [3] [4] [5] [6] [7] [8]

Last update Sat Jun 2 20:57:36 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page