Yoshinobu Higami

	2012
45		Yoshinobu Higami, Satoshi Ohno, Hironori Yamaoka, Hiroshi Takahashi, Yoshihiro Shimizu, Takashi Aikyo: Generation of Diagnostic Tests for Transition Faults Using a Stuck-At ATPG Tool. IEICE Transactions 95-D(4): 1093-1100 (2012)
	2011
44		Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja: Fault simulation and test generation for clock delay faults. ASP-DAC 2011: 799-805
43		Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja: On Detecting Transition Faults in the Presence of Clock Delay Faults. Asian Test Symposium 2011: 1-6
42		Yoshinobu Higami, Hiroshi Furutani, Takao Sakai, Shuichi Kameyama, Hiroshi Takahashi: Test Pattern Selection for Defect-Aware Test. Asian Test Symposium 2011: 102-107
41		Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja: Enhancement of Clock Delay Faults Testing. European Test Symposium 2011: 216
	2010
40		Kouji Hirata, Khamisi Kalegele, Yoshinobu Higami, Shin-ya Kobayashi: Dynamic Parallel Downloading with Network Coding in $\lambda$-Grid Networks. JCM 5(5): 425-435 (2010)
39		Kouji Hirata, Khamisi Kalegele, Yoshinobu Higami, Shin-ya Kobayashi: Replica Selection and Downloading based on Wavelength Availability in λ-grid Networks. JCM 5(9): 692-702 (2010)
	2009
38		Hiroshi Takahashi, Yoshinobu Higami, Yuzo Takamatsu, Koji Yamazaki, Toshiyuki Tsutsumi, Hiroyuki Yotsuyanagi, Masaki Hashizume: New Class of Tests for Open Faults with Considering Adjacent Lines. Asian Test Symposium 2009: 301-306
37		Yoshinobu Higami, Yosuke Kurose, Satoshi Ohno, Hironori Yamaoka, Hiroshi Takahashi, Yoshihiro Shimizu, Takashi Aikyo, Yuzo Takamatsu: Diagnostic test generation for transition faults using a stuck-at ATPG tool. ITC 2009: 1-9
36		Koji Yamazaki, Toshiyuki Tsutsumi, Hiroshi Takahashi, Yoshinobu Higami, Takashi Aikyo, Yuzo Takamatsu, Hiroyuki Yotsuyanagi, Masaki Hashizume: A Novel Approach for Improving the Quality of Open Fault Diagnosis. VLSI Design 2009: 85-90
35		Hiroyuki Yotsuyanagi, Masaki Hashizume, Toshiyuki Tsutsumi, Koji Yamazaki, Takashi Aikyo, Yoshinobu Higami, Hiroshi Takahashi, Yuzo Takamatsu: Fault Effect of Open Faults Considering Adjacent Signal Lines in a 90 nm IC. VLSI Design 2009: 91-96
34		Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu: Addressing Defect Coverage through Generating Test Vectors for Transistor Defects. IEICE Transactions 92-A(12): 3128-3135 (2009)
	2008
33		Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu: Maximizing Stuck-Open Fault Coverage Using Stuck-at Test Vectors. IEICE Transactions 91-A(12): 3506-3513 (2008)
32		Yuzo Takamatsu, Hiroshi Takahashi, Yoshinobu Higami, Takashi Aikyo, Koji Yamazaki: Fault Diagnosis on Multiple Fault Models by Using Pass/Fail Information. IEICE Transactions 91-D(3): 675-682 (2008)
31		Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu: Fault Simulation and Test Generation for Transistor Shorts Using Stuck-at Test Tools. IEICE Transactions 91-D(3): 690-699 (2008)
30		Hiroshi Takahashi, Yoshinobu Higami, Shuhei Kadoyama, Yuzo Takamatsu, Koji Yamazaki, Takashi Aikyo, Yasuo Sato: Post-BIST Fault Diagnosis for Multiple Faults. IEICE Transactions 91-D(3): 771-775 (2008)
	2007
29		Takashi Aikyo, Hiroshi Takahashi, Yoshinobu Higami, Junichi Ootsu, Kyohei Ono, Yuzo Takamatsu: Timing-Aware Diagnosis for Small Delay Defects. DFT 2007: 223-234
28		Hiroshi Takahashi, Yoshinobu Higami, Toru Kikkawa, Takashi Aikyo, Yuzo Takamatsu, Hiroyuki Yotsuyanagi, Masaki Hashizume: Test Generation and Diagnostic Test Generation for Open Faults with Considering Adjacent Lines. DFT 2007: 243-251
27		Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Yuzo Takamatsu: Fault Coverage and Fault Efficiency of Transistor Shorts using Gate-Level Simulation and Test Generation. VLSI Design 2007: 781-786
	2006
26		Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu: Compaction of pass/fail-based diagnostic test vectors for combinational and sequential circuits. ASP-DAC 2006: 659-664
25		Hiroshi Takahashi, Shuhei Kadoyama, Yoshinobu Higami, Yuzo Takamatsu, Koji Yamazaki, Takashi Aikyo, Yasuo Sato: Effective Post-BIST Fault Diagnosis for Multiple Faults. DFT 2006: 401-109
24		Yoshinobu Higami, Seiji Kajihara, Irith Pomeranz, Shin-ya Kobayashi, Yuzo Takamatsu: On Finding Don't Cares in Test Sequences for Sequential Circuits. IEICE Transactions 89-D(11): 2748-2755 (2006)
	2005
23		T. Seiyama, Hiroshi Takahashi, Yoshinobu Higami, Kazuo Yamazaki, Yuzo Takamatsu: On the fault diagnosis in the presence of unknown fault models using pass/fail information. ISCAS (3) 2005: 2987-2990
22		Yoshinobu Higami, Seiji Kajihara, Hideyuki Ichihara, Yuzo Takamatsu: Test cost reduction for logic circuits: Reduction of test data volume and test application time. Systems and Computers in Japan 36(6): 69-83 (2005)
	2004
21		Hiroshi Takahashi, Yukihiro Yamamoto, Yoshinobu Higami, Yuzo Takamatsu: Enhancing BIST Based Single/Multiple Stuck-at Fault Diagnosis by Ambiguous Test Set. Asian Test Symposium 2004: 216-221
20		Yuichi Sato, Hiroshi Takahashi, Yoshinobu Higami, Yuzo Takamatsu: Failure Analysis of Open Faults by Using Detecting/Un-detecting Information on Tests. Asian Test Symposium 2004: 222-227
19		Yoshinobu Higami, Seiji Kajihara, Shin-ya Kobayashi, Yuzo Takamatsu: Techniques for Finding Xs in Test Sequences for Sequential Circuits and Applications to Test Length/Power Reduction. Asian Test Symposium 2004: 46-49
18		Yoshinobu Higami, Shin-ya Kobayashi, Yuzo Takamatsu: Generation of Test Sequences with Low Power Dissipation for Sequential Circuits. IEICE Transactions 87-D(3): 530-536 (2004)
	2003
17		Yoshinobu Higami, Shin-ya Kobayashi, Yuzo Takamatsu, Seiji Kajihara, Irith Pomeranz: A Method to Find Don't Care Values in Test Sequences for Sequential Circuits. ICCD 2003: 397-
	2002
16		Yoshinobu Higami, Shin-ya Kobayashi, Yuzo Takamatsu: A Method to Reduce Power Dissipation during Test for Sequential Circuits. Asian Test Symposium 2002: 326-331
15		Yoshinobu Higami, Shin-ya Kobayashi, Yuzo Takamatsu: Modifying Test Vectors for Reducing Power Dissipation in CMOS Circuits. DELTA 2002: 431-433
	2001
14		Hiroshi Takahashi, Marong Phadoongsidhi, Yoshinobu Higami, Kewal K. Saluja, Yuzo Takamatsu: Simulation-Based Diagnosis for Crosstalk Faults in Sequential Circuits. Asian Test Symposium 2001: 63-
13		Yoshinobu Higami, Naoko Takahashi, Yuzo Takamatsu: Test Generation for Double Stuck-at Faults. Asian Test Symposium 2001: 71-75
	2000
12		Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita: Fault models and test generation for IDDQ testing: embedded tutorial. ASP-DAC 2000: 509-514
11		Yoshinobu Higami, Yuzo Takamatsu, Kozo Kinoshita: Test sequence compaction for sequential circuits with reset states. Asian Test Symposium 2000: 165-170
10		Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita: Algorithms to Select IDDQ Measurement Vectors for Bridging Faults in Sequential Circuits. J. Electronic Testing 16(5): 443-451 (2000)
9		Yoshinobu Higami, Kewal K. Saluja, Yuzo Takamatsu, Kozo Kinoshita: Static test compaction for IDDQ testing of bridging faults in sequential circuits. Systems and Computers in Japan 31(11): 41-50 (2000)
	1999
8		Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita: Fault Simulation Techniques to Reduce IDDQ Measurement Vectors for Sequential Circuits. Asian Test Symposium 1999: 141-146
7		Yoshinobu Higami, Kewal K. Saluja, Kozo Kinoshita: Efficient Techniques for Reducing IDDQ Observation Time for Sequential Circuits. VLSI Design 1999: 72-77
	1998
6		Yoshinobu Higami, Kewal K. Saluja, Kozo Kinoshita: Observation Time Reduction for IDDQ Testing of Briding Faults in Sequential Circuits. Asian Test Symposium 1998: 312-317
	1997
5		Yoshinobu Higami, Kozo Kinoshita: Design of partially parallel scan chain. ED&TC 1997: 626
	1996
4		Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita: Partially Parallel Scan Chain for Test Length Reduction by Using Retiming Technique. Asian Test Symposium 1996: 94-99
	1995
3		Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita: Test sequence compaction by reduced scan shift and retiming. Asian Test Symposium 1995: 169-175
2		Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita: Partial scan design and test sequence generation based on reduced scan shift method. J. Electronic Testing 7(1-2): 115-124 (1995)
	1994
1		Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita: Reduced Scan Shift: A New Testing Method for Sequential Circuit. ITC 1994: 624-630

Coauthor Index

1	Takashi Aikyo	[25] [28] [29] [30] [32] [35] [36] [37] [45]
2	Hiroshi Furutani	[42]
3	Masaki Hashizume	[28] [35] [36] [38]
4	Kouji Hirata	[39] [40]
5	Hideyuki Ichihara	[22]
6	Shuhei Kadoyama	[25] [30]
7	Seiji Kajihara	[1] [2] [3] [4] [17] [19] [22] [24]
8	Khamisi Kalegele	[39] [40]
9	Shuichi Kameyama	[42]
10	Toru Kikkawa	[28]
11	Kozo Kinoshita	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
12	Shin-ya Kobayashi	[15] [16] [17] [18] [19] [24] [26] [31] [33] [34] [39] [40] [41] [43] [44]
13	Yosuke Kurose	[37]
14	Satoshi Ohno	[37] [45]
15	Kyohei Ono	[29]
16	Junichi Ootsu	[29]
17	Marong Phadoongsidhi	[14]
18	Irith Pomeranz	[17] [24]
19	Takao Sakai	[42]
20	Kewal K. Saluja	[6] [7] [8] [9] [10] [12] [14] [26] [27] [31] [33] [34] [41] [43] [44]
21	Yasuo Sato	[25] [30]
22	Yuichi Sato	[20]
23	T. Seiyama	[23]
24	Yoshihiro Shimizu	[37] [45]
25	Hiroshi Takahashi	[14] [20] [21] [23] [25] [26] [27] [28] [29] [30] [31] [32] [33] [34] [35] [36] [37] [38] [41] [42] [43] [44] [45]
26	Naoko Takahashi	[13]
27	Yuzo Takamatsu	[8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [25] [26] [27] [28] [29] [30] [31] [32] [33] [34] [35] [36] [37] [38]
28	Toshiyuki Tsutsumi	[35] [36] [38]
29	Yukihiro Yamamoto	[21]
30	Hironori Yamaoka	[37] [45]
31	Kazuo Yamazaki	[23]
32	Koji Yamazaki	[25] [30] [32] [35] [36] [38]
33	Hiroyuki Yotsuyanagi	[28] [35] [36] [38]

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