 | 2011 |
|---|
| 6 |       | Yasuo Hidaka,
Takeshi Horie,
Yoichi Koyanagi,
Takashi Miyoshi,
Hideki Osone,
Samir Parikh,
Subodh M. Reddy,
Toshiyuki Shibuya,
Yasushi Umezawa,
William W. Walker:
A 4-channel 10.3Gb/s transceiver with adaptive phase equalizer for 4-to-41dB loss PCB channel.
ISSCC 2011: 346-348 |
| 2009 |
|---|
| 5 | | Yasuo Hidaka,
Weixin Gai,
Takeshi Horie,
Jian Hong Jiang,
Yoichi Koyanagi,
Hideki Osone:
A 4-channel 10.3Gb/s backplane transceiver macro with 35dB equalizer and sign-based zero-forcing adaptive control.
ISSCC 2009: 188-189 |
| 2007 |
|---|
| 4 | | Jian Hong Jiang,
Weixin Gai,
Akira Hattori,
Yasuo Hidaka,
Takeshi Horie,
Yoichi Koyanagi,
Hideki Osone:
Design Consideration of 6.25 Gbps Signaling for High-Performance Server.
ASP-DAC 2007: 854-857 |
| 1993 |
|---|
| 3 | | Yasuo Hidaka,
Hanpei Koike,
Hidehiko Tanaka:
Multiple Threads in Cyclic Register Windows.
ISCA 1993: 131-142 |
| 1992 |
|---|
| 2 | | Yasuo Hidaka,
Hanpei Koike,
Hidehiko Tanaka:
Architecture of Parallel Management Kernel for PIE64.
PARLE 1992: 685-700 |
| 1991 |
|---|
| 1 |  | Yasuo Hidaka,
Hanpei Koike,
Jun'ichi Tatemura,
Hidehiko Tanaka:
A Static Load Partitioning Method based on Execution Profile for Committed Choice Languages.
ISLP 1991: 470-484 |
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