 | 2005 |
|---|
| 7 |       | Iain Robertson,
Graham Hetherington,
Tom Leslie,
Ishwar Parulkar,
Ronald Lesnikoski:
Testing high-speed, large scale implementation of SerDes I/Os on chips used in throughput computing systems.
ITC 2005: 8 |
| 2004 |
|---|
| 6 | | C. P. Ravikumar,
Graham Hetherington:
A Holistic Parallel and Hierarchical Approach towards Design-For-Test.
ITC 2004: 345-354 |
| 5 | | Kenneth M. Butler,
Jayashree Saxena,
Tony Fryars,
Graham Hetherington:
Minimizing Power Consumption in Scan Testing: Pattern Generation and DFT Techniques.
ITC 2004: 355-364 |
| 2003 |
|---|
| 4 | | Graham Hetherington,
Richard Simpson:
Circular BIST testing the digital logic within a high speed Serdes.
ITC 2003: 1221-1228 |
| 1999 |
|---|
| 3 | | Graham Hetherington,
Tony Fryars,
Nagesh Tamarapalli,
Mark Kassab,
Abu S. M. Hassan,
Janusz Rajski:
Logic BIST for large industrial designs: real issues and case studies.
ITC 1999: 358-367 |
| 1995 |
|---|
| 2 | | Graham Hetherington,
Greg Sutton,
Kenneth M. Butler,
Theo J. Powell:
Test Generation and Design for Test for a Large Multiprocessing DSP.
ITC 1995: 149-156 |
| 1990 |
|---|
| 1 | | Robin C. Sarma,
Mark D. Dooley,
N. Craig Newman,
Graham Hetherington:
High-Level Synthesis: Technology Transfer to Industry.
DAC 1990: 549-554 |
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