Tomas Herrman

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2008

3 Jaroslav Skarvada, Zdenek Kotásek, Tomas Herrman: Power Conscious RTL Test Scheduling. DSD 2008: 721-728

2 Jaroslav Skarvada, Zdenek Kotásek, Tomas Herrman: Testability analysis based on the identification of testable blocks with predefined properties. Microprocessors and Microsystems - Embedded Hardware Design 32(5-6): 296-302 (2008)

2007

1 Jaroslav Skarvada, Tomas Herrman, Zdenek Kotásek: Testability Analysis Based on the Identification of Testable Blocks with Predefined Properties. DSD 2007: 611-618

	2008
3		Jaroslav Skarvada, Zdenek Kotásek, Tomas Herrman: Power Conscious RTL Test Scheduling. DSD 2008: 721-728
2		Jaroslav Skarvada, Zdenek Kotásek, Tomas Herrman: Testability analysis based on the identification of testable blocks with predefined properties. Microprocessors and Microsystems - Embedded Hardware Design 32(5-6): 296-302 (2008)
	2007
1		Jaroslav Skarvada, Tomas Herrman, Zdenek Kotásek: Testability Analysis Based on the Identification of Testable Blocks with Predefined Properties. DSD 2007: 611-618

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