Bjørnar Hernes

	2007
3		Terje N. Andersen, Atle Briskemyr, Frode Telstø, Johnny Bjørnsen, Thomas E. Bonnerud, Bjørnar Hernes, Øystein Moldsvor: A 97mW 110MS/s 12b Pipeline ADC Implemented in 0.18$\mu$m Digital CMOS CoRR abs/0710.4839: (2007)
	2004
2		Terje N. Andersen, Atle Briskemyr, Frode Telstø, Johnny Bjørnsen, Thomas E. Bonnerud, Bjørnar Hernes, Øystein Moldsvor: A 97mW 110MS/s 12b Pipeline ADC Implemented in 0.18mum Digital CMOS. DATE 2004: 219-222
	2001
1		Bjørnar Hernes, Øystein Moldsvor, T. Saether: A -80 dB HD3 opamp in 3.3 V CMOS technology using tail current compensation. ISCAS (1) 2001: 216-219

Coauthor Index

1	Terje N. Andersen	[2] [3]
2	Johnny Bjørnsen	[2] [3]
3	Thomas E. Bonnerud	[2] [3]
4	Atle Briskemyr	[2] [3]
5	Øystein Moldsvor	[1] [2] [3]
6	T. Saether	[1]
7	Frode Telstø	[2] [3]

Last update Sat Jun 2 20:57:36 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page