 | 2010 |
|---|
| 8 |       | Uksong Kang,
Hoeju Chung,
Seongmoo Heo,
Dukha Park,
Hoon Lee,
Jin Ho Kim,
Soon-Hong Ahn,
Sooho Cha,
Jaesung Ahn,
Dukmin Kwon,
Jaewook Lee,
Han-Sung Joo,
Woo-Seop Kim,
Dong Hyeon Jang,
Nam-Seog Kim,
Jung-Hwan Choi,
Tae-Gyeong Chung,
Jei-Hwan Yoo,
Joo-Sun Choi,
Changhyun Kim,
Young-Hyun Jun:
8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology.
J. Solid-State Circuits 45(1): 111-119 (2010) |
| 2009 |
|---|
| 7 | | Uksong Kang,
Hoeju Chung,
Seongmoo Heo,
Soon-Hong Ahn,
Hoon Lee,
Sooho Cha,
Jaesung Ahn,
Dukmin Kwon,
Jin Ho Kim,
Jaewook Lee,
Han-Sung Joo,
Woo-Seop Kim,
Hyun-Kyung Kim,
Eun-Mi Lee,
So-Ra Kim,
Keum-Hee Ma,
Dong-Hyun Jang,
Nam-Seog Kim,
Man-Sik Choi,
Sae-Jang Oh,
Jung-Bae Lee,
Tae-Kyung Jung,
Jei-Hwan Yoo,
Changhyun Kim:
8Gb 3D DDR3 DRAM using through-silicon-via technology.
ISSCC 2009: 130-131 |
| 2007 |
|---|
| 6 | | Seongmoo Heo,
Ronny Krashinsky,
Krste Asanovic:
Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy.
IEEE Trans. VLSI Syst. 15(9): 1060-1064 (2007) |
| 2005 |
|---|
| 5 | | Seongmoo Heo,
Krste Asanovic:
Replacing global wires with an on-chip network: a power analysis.
ISLPED 2005: 369-374 |
| 2004 |
|---|
| 4 | | Seongmoo Heo,
Krste Asanovic:
Power-optimal pipelining in deep submicron technology.
ISLPED 2004: 218-223 |
| 2003 |
|---|
| 3 | | Seongmoo Heo,
Kenneth C. Barr,
Krste Asanovic:
Reducing power density through activity migration.
ISLPED 2003: 217-222 |
| 2002 |
|---|
| 2 | | Seongmoo Heo,
Kenneth C. Barr,
Mark Hampton,
Krste Asanovic:
Dynamic Fine-Grain Leakage Reduction Using Leakage-Biased Bitlines.
ISCA 2002: 137-147 |
| 2001 |
|---|
| 1 | | Seongmoo Heo,
Ronny Krashinsky,
Krste Asanovic:
Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy.
ARVLSI 2001: 59-74 |
Data released under the ODC-BY 1.0 license — See also our legal information page