Khaled R. Heloue

	2012
10		Khaled R. Heloue, Sari Onaissi, Farid N. Najm: Efficient Block-Based Parameterized Timing Analysis Covering All Potentially Critical Paths. IEEE Trans. on CAD of Integrated Circuits and Systems 31(4): 472-484 (2012)
	2009
9		Sari Onaissi, Khaled R. Heloue, Farid N. Najm: Clock skew optimization via wiresizing for timing sign-off covering all process corners. DAC 2009: 196-201
8		Khaled R. Heloue, Chandramouli V. Kashyap, Farid N. Najm: Quantifying robustness metrics in parameterized static timing analysis. ICCAD 2009: 209-216
7		Sari Onaissi, Khaled R. Heloue, Farid N. Najm: PSTA-based branch and bound approach to the silicon speedpath isolation problem. ICCAD 2009: 217-224
6		Khaled R. Heloue, Navid Azizi, Farid N. Najm: Full-Chip Model for Leakage-Current Estimation Considering Within-Die Correlation. IEEE Trans. on CAD of Integrated Circuits and Systems 28(6): 874-887 (2009)
	2008
5		Khaled R. Heloue, Farid N. Najm: Parameterized timing analysis with general delay models and arbitrary variation sources. DAC 2008: 403-408
4		Khaled R. Heloue, Sari Onaissi, Farid N. Najm: Efficient block-based parameterized timing analysis covering all potentially critical paths. ICCAD 2008: 173-180
3		Khaled R. Heloue, Farid N. Najm: Early Analysis and Budgeting of Margins and Corners Using Two-Sided Analytical Yield Models. IEEE Trans. on CAD of Integrated Circuits and Systems 27(10): 1826-1839 (2008)
	2007
2		Khaled R. Heloue, Navid Azizi, Farid N. Najm: Modeling and Estimation of Full-Chip Leakage Current Considering Within-Die Correlation. DAC 2007: 93-98
	2005
1		Khaled R. Heloue, Farid N. Najm: Statistical timing analysis with two-sided constraints. ICCAD 2005: 829-836

Coauthor Index

1	Navid Azizi	[2] [6]
2	Chandramouli V. Kashyap	[8]
3	Farid N. Najm	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10]
4	Sari Onaissi	[4] [7] [9] [10]

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