Nils Hedenstierna

	1993
5		Nils Hedenstierna, Kjell O. Jeppson: Comments on `A module generator for optimized CMOS buffers'. IEEE Trans. on CAD of Integrated Circuits and Systems 12(1): 180-181 (1993)
4		Kjell O. Jeppson, Sven Christensson, Nils Hedenstierna: Formal definitions of edge-based geometric design rules. IEEE Trans. on CAD of Integrated Circuits and Systems 12(1): 59-69 (1993)
3		Nils Hedenstierna, Kjell O. Jeppson: The halo algorithm-an algorithm for hierarchical design of rule checking of VLSI circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 12(2): 265-272 (1993)
	1989
2		Nils Hedenstierna, Kjell O. Jeppson: The Use of Inverse Layout Trees for Hierarchical Design Rule Checking. DAC 1989: 508-512
	1987
1		Nils Hedenstierna, Kjell O. Jeppson: CMOS Circuit Speed and Buffer Optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 6(2): 270-281 (1987)

Coauthor Index

1	Sven Christensson	[4]
2	Kjell O. Jeppson	[1] [2] [3] [4] [5]

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