Wei-Feng He

	2011
3		Jian-Fei Jiang, Xu Wang, Wei-Guang Sheng, Wei-Feng He, Zhi-Gang Mao: A clock-less transceiver for global interconnect. VLSI-SoC 2011: 184-187
	2007
2		Wei-Feng He, Zhi-Gang Mao: An Improved Frame-Level Pipelined Architecture for High Resolution Video Motion Estimation. ISCAS 2007: 1381-1384
1		Wei-Feng He, Meng-Lian Zhao, Chi-Ying Tsui, Zhi-Gang Mao: A Scalable Frame-Level Pipelined Architecture for FSBM Motion Estimation. VLSI Design 2007: 830-835

Coauthor Index

1	Jian-Fei Jiang	[3]
2	Zhi-Gang Mao	[1] [2] [3]
3	Wei-Guang Sheng	[3]
4	Chi-Ying Tsui	[1]
5	Xu Wang	[3]
6	Meng-Lian Zhao	[1]

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