 | 2011 |
|---|
| 8 |       | Ku He,
Andreas Gerstlauer,
Michael Orshansky:
Controlled timing-error acceptance for low energy IDCT design.
DATE 2011: 758-763 |
| 7 | | Yu Wang,
Hong Luo,
Ku He,
Rong Luo,
Huazhong Yang,
Yuan Xie:
Temperature-Aware NBTI Modeling and the Impact of Standby Leakage Reduction Techniques on Circuit Performance Degradation.
IEEE Trans. Dependable Sec. Comput. 8(5): 756-769 (2011) |
| 2009 |
|---|
| 6 | | Ashish Kumar Singh,
Ku He,
Constantine Caramanis,
Michael Orshansky:
Mitigation of intra-array SRAM variability using adaptive voltage architecture.
ICCAD 2009: 637-644 |
| 2008 |
|---|
| 5 | | Yu Wang,
Ku He,
Rong Luo,
Hui Wang,
Huazhong Yang:
Two-Phase Fine-Grain Sleep Transistor Insertion Technique in Leakage Critical Circuits.
IEEE Trans. VLSI Syst. 16(9): 1101-1113 (2008) |
| 2007 |
|---|
| 4 | | Yu Wang,
Hong Luo,
Ku He,
Rong Luo,
Huazhong Yang,
Yuan Xie:
Temperature-aware NBTI modeling and the impact of input vector control on performance degradation.
DATE 2007: 546-551 |
| 3 | | Ku He,
Rong Luo,
Yu Wang:
A power gating scheme for ground bounce reduction during mode transition.
ICCD 2007: 388-394 |
| 2 | | Hong Luo,
Yu Wang,
Ku He,
Rong Luo,
Huazhong Yang,
Yuan Xie:
Modeling of PMOS NBTI Effect Considering Temperature Variation.
ISQED 2007: 139-144 |
| 1 | | Hong Luo,
Yu Wang,
Ku He,
Rong Luo,
Huazhong Yang,
Yuan Xie:
A Novel Gate-Level NBTI Delay Degradation Model with Stacking Effect.
PATMOS 2007: 160-170 |
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