Yasushi Hayakawa

	2011
2		Sugako Otani, Hiroyuki Kondo, Itaru Nonomura, Atsuyuki Ikeya, Minoru Uemura, Yasushi Hayakawa, Takeshi Oshita, Satoshi Kaneko, Katsushi Asahina, Kazutami Arimoto, Shin'ichi Miura, Toshihiro Hanawa, Taisuke Boku, Mitsuhisa Sato: An 80Gb/s dependable communication SoC with PCI express I/F and 8 CPUs. ISSCC 2011: 266-268
	1998
1		Koji Nii, Hiroshi Makino, Yoshiki Tujihashi, Chikayoshi Morishima, Yasushi Hayakawa, Hiroyuki Nunogami, Takahiko Arakawa, Hisanori Hamano: A low power SRAM using auto-backgate-controlled MT-CMOS. ISLPED 1998: 293-298

Coauthor Index

1	Takahiko Arakawa	[1]
2	Kazutami Arimoto	[2]
3	Katsushi Asahina	[2]
4	Taisuke Boku	[2]
5	Hisanori Hamano	[1]
6	Toshihiro Hanawa	[2]
7	Atsuyuki Ikeya	[2]
8	Satoshi Kaneko	[2]
9	Hiroyuki Kondo	[2]
10	Hiroshi Makino	[1]
11	Shin'ichi Miura	[2]
12	Chikayoshi Morishima	[1]
13	Koji Nii	[1]
14	Itaru Nonomura	[2]
15	Hiroyuki Nunogami	[1]
16	Takeshi Oshita	[2]
17	Sugako Otani	[2]
18	Mitsuhisa Sato	[2]
19	Yoshiki Tujihashi	[1]
20	Minoru Uemura	[2]

Last update Fri Jun 1 15:44:53 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page