Kazumi Hatayama

	2011
23		Kohei Miyase, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Yuta Yamato, Hiroshi Furukawa, Xiaoqing Wen, Seiji Kajihara: Distribution-Controlled X-Identification for Effective Reduction of Launch-Induced IR-Drop in At-Speed Scan Testing. IEICE Transactions 94-D(6): 1216-1226 (2011)
	2010
22		Takumi Uezono, Tomoyuki Takahashi, Michihiro Shintani, Kazumi Hatayama, Kazuya Masu, Hiroyuki Ochi, Takashi Sato: Scan based process parameter estimation through path-delay inequalities. ISCAS 2010: 3553-3556
21		Takumi Uezono, Tomoyuki Takahashi, Michihiro Shintani, Kazumi Hatayama, Kazuya Masu, Hiroyuki Ochi, Takashi Sato: Path clustering for adaptive test. VTS 2010: 15-20
20		Kohei Miyase, Xiaoqing Wen, Seiji Kajihara, Yuta Yamato, Atsushi Takashima, Hiroshi Furukawa, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Kewal K. Saluja: A Study of Capture-Safe Test Generation Flow for At-Speed Testing. IEICE Transactions 93-A(7): 1309-1318 (2010)
19		Kazumi Hatayama, Tsuyoshi Shinogi: Foreword. IEICE Transactions 93-D(1): 1 (2010)
	2009
18		Michihiro Shintani, Takumi Uezono, Tomoyuki Takahashi, Hiroyuki Ueyama, Takashi Sato, Kazumi Hatayama, Takashi Aikyo, Kazuya Masu: An Adaptive Test for Parametric Faults Based on Statistical Timing Information. Asian Test Symposium 2009: 151-156
17		Kohei Miyase, Yuta Yamato, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Xiaoqing Wen, Seiji Kajihara: A novel post-ATPG IR-drop reduction scheme for at-speed scan testing in broadcast-scan-based test compression environment. ICCAD 2009: 97-104
16		Masayuki Arai, Akifumi Suto, Kazuhiko Iwasaki, Katsuyuki Nakano, Michihiro Shintani, Kazumi Hatayama, Takashi Aikyo: Small Delay Fault Model for Intra-Gate Resistive Open Defects. VTS 2009: 27-32
	2008
15		X. Wen, Kohei Miyase, Seiji Kajihara, Hiroshi Furukawa, Yuta Yamato, Atsushi Takashima, Kenji Noda, H. Ito, Kazumi Hatayama, Takashi Aikyo, Kewal K. Saluja: A Capture-Safe Test Generation Scheme for At-Speed Scan Testing. European Test Symposium 2008: 55-60
14		Kohei Miyase, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Yuta Yamato, Hiroshi Furukawa, Xiaoqing Wen, Seiji Kajihara: Effective IR-drop reduction in at-speed scan testing using Distribution-Controlling X-Identification. ICCAD 2008: 52-58
	2007
13		Seiji Kajihara, Shohei Morishima, Masahiro Yamamoto, Xiaoqing Wen, Masayasu Fukunaga, Kazumi Hatayama, Takashi Aikyo: Estimation of delay test quality and its application to test generation. ICCAD 2007: 413-417
	2006
12		Kazumi Hatayama: Session Abstract. VTS 2006: 200-201
	2004
11		Kazumi Hatayama, Rochit Rajsuman: Opportunities with the open architecture test system. ASP-DAC 2004: 334
	2002
10		Kazumi Hatayama, Michinobu Nakao, Yasuo Sato: At-Speed Built-in Test for Logic Circuits with Multiple Clocks. Asian Test Symposium 2002: 292-297
9		Kazumi Hatayama, Michinobu Nakao, Yoshikazu Kiyoshige, Koichiro Natsume, Yasuo Sato, Takaharu Nagumo: Application of High-Quality Built-In Test to Industrial Designs. ITC 2002: 1003-1012
	2001
8		Michinobu Nakao, Yoshikazu Kiyoshige, Kazumi Hatayama, Yasuo Sato, Takaharu Nagumo: Test Generation for Multiple-Threshold Gate-Delay Fault Model. Asian Test Symposium 2001: 244-
	1999
7		Michinobu Nakao, Seiji Kobayashi, Kazumi Hatayama, Kazuhiko Iijima, Seiji Terada: Low overhead test point insertion for scan-based BIST. ITC 1999: 348-357
	1997
6		Kazumi Hatayama, Mitsuji Ikeda, Masahiro Takakura, Satoshi Uchiyama, Yoriyuki Sakamoto: Application of a Design for Delay Testability Approach to High Speed Logic LSIs. Asian Test Symposium 1997: 112-115
5		Michinobu Nakao, Kazumi Hatayama, Isao Higashi: Accelerated Test Points Selection Method for Scan-Based BIST. Asian Test Symposium 1997: 359-
4		Kazumi Hatayama, Kazunori Hikone, T. Miyazaki, H. Yamada: A practical approach to instruction-based test generation for functional modules of VLSI processors. VTS 1997: 17-23
	1995
3		Hiroshi Date, Michinobu Nakao, Kazumi Hatayama: A parallel sequential test generation system DESCARTES based on real-valued logic simulation. Asian Test Symposium 1995: 252-258
	1992
2		Kazumi Hatayama, Kazunori Hikone, Mitsuji Ikeda, Terumine Hayashi: Sequential Test Generation Based on Real-Value Logic. ITC 1992: 41-48
	1989
1		Kazumi Hatayama, Mitsuji Ikeda, Terumine Hayashi, Masahiro Takakura, Kuniaki Kishida, Shun Ishiyama: Enhanced Delay Test Generator for High-Speed Logic LSIs. ITC 1989: 161-165

Coauthor Index

1	Takashi Aikyo	[13] [14] [15] [16] [17] [18] [20] [23]
2	Masayuki Arai	[16]
3	Hiroshi Date	[3]
4	Masayasu Fukunaga	[13]
5	Hiroshi Furukawa	[14] [15] [20] [23]
6	Terumine Hayashi	[1] [2]
7	Isao Higashi	[5]
8	Kazunori Hikone	[2] [4]
9	Kazuhiko Iijima	[7]
10	Mitsuji Ikeda	[1] [2] [6]
11	Shun Ishiyama	[1]
12	H. Ito	[15]
13	Hideaki Ito	[14] [17] [20] [23]
14	Kazuhiko Iwasaki	[16]
15	Seiji Kajihara	[13] [14] [15] [17] [20] [23]
16	Kuniaki Kishida	[1]
17	Yoshikazu Kiyoshige	[8] [9]
18	Seiji Kobayashi	[7]
19	Kazuya Masu	[18] [21] [22]
20	Kohei Miyase	[14] [15] [17] [20] [23]
21	T. Miyazaki	[4]
22	Shohei Morishima	[13]
23	Takaharu Nagumo	[8] [9]
24	Katsuyuki Nakano	[16]
25	Michinobu Nakao	[3] [5] [7] [8] [9] [10]
26	Koichiro Natsume	[9]
27	Kenji Noda	[14] [15] [17] [20] [23]
28	Hiroyuki Ochi	[21] [22]
29	Rochit Rajsuman	[11]
30	Yoriyuki Sakamoto	[6]
31	Kewal K. Saluja	[15] [20]
32	Takashi Sato	[18] [21] [22]
33	Yasuo Sato	[8] [9] [10]
34	Tsuyoshi Shinogi	[19]
35	Michihiro Shintani	[16] [18] [21] [22]
36	Akifumi Suto	[16]
37	Tomoyuki Takahashi	[18] [21] [22]
38	Masahiro Takakura	[1] [6]
39	Atsushi Takashima	[15] [20]
40	Seiji Terada	[7]
41	Satoshi Uchiyama	[6]
42	Hiroyuki Ueyama	[18]
43	Takumi Uezono	[18] [21] [22]
44	X. Wen	[15]
45	Xiaoqing Wen	[13] [14] [17] [20] [23]
46	H. Yamada	[4]
47	Masahiro Yamamoto	[13]
48	Yuta Yamato	[14] [15] [17] [20] [23]

Colors in the list of coauthors

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