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| 2012 | ||
|---|---|---|
| 39 | Nauman H. Khan, Soha Hassoun: The feasibility of Carbon Nanotubes for power delivery in 3-D Integrated Circuits. ASP-DAC 2012: 53-58 | |
| 38 | Soha Hassoun: Genetic/bio design automation for (re-)engineering biological systems. DATE 2012: 242-247 | |
| 2011 | ||
| 37 | Leon Stok, Nikil D. Dutt, Soha Hassoun: Proceedings of the 48th Design Automation Conference, DAC 2011, San Diego, California, USA, June 5-10, 2011 ACM 2011 | |
| 36 | Nauman H. Khan, Syed M. Alam, Soha Hassoun: Mitigating TSV-induced substrate noise in 3-D ICs using GND plugs. ISQED 2011: 751-756 | |
| 35 | Nauman H. Khan, Syed M. Alam, Soha Hassoun: Power Delivery Design for 3-D ICs Using Different Through-Silicon Via (TSV) Technologies. IEEE Trans. VLSI Syst. 19(4): 647-658 (2011) | |
| 34 | Gautham Vivek Sridharan, Soha Hassoun, Kyongbum Lee: Identification of Biochemical Network Modules Based on Shortest Retroactive Distances. PLoS Computational Biology 7(11): (2011) | |
| 2010 | ||
| 33 | Nauman H. Khan, Sherief Reda, Soha Hassoun: Early estimation of TSV area for power delivery in 3-D integrated circuits. 3DIC 2010: 1-6 | |
| 32 | Marc Riedel, Soha Hassoun, Ron Weiss, Pamela Silver, J. Christopher Anderson, Richard M. Murray: Joint DAC/IWBDA special session engineering biology: fundamentals and applications. DAC 2010: 220-221 | |
| 31 | Jinhai Qiu, Sherief Reda, Soha Hassoun: Fast, accurate a priori routing delay estimation. SLIP 2010: 77-82 | |
| 2009 | ||
| 30 | Nauman H. Khan, Syed M. Alam, Soha Hassoun: System-level comparison of power delivery design for 2D and 3D ICs. 3DIC 2009: 1-7 | |
| 29 | Nauman H. Khan, Syed M. Alam, Soha Hassoun: Through-Silicon Via (TSV)-induced noise characterization and noise mitigation using coaxial TSVs. 3DIC 2009: 1-7 | |
| 28 | John Rieffel, Frank Saunders, Shilpa Nadimpalli, Harvey Zhou, Soha Hassoun, Jason Rife, Barry Trimmer: Evolving soft robotic locomotion in PhysX. GECCO (Companion) 2009: 2499-2504 | |
| 27 | Ehsan Ullah, Kyongbum Lee, Soha Hassoun: An algorithm for identifying dominant-edge metabolic pathways. ICCAD 2009: 144-150 | |
| 2008 | ||
| 26 | Brian Swahn, Soha Hassoun: Electro-Thermal Analysis of Multi-Fin Devices. IEEE Trans. VLSI Syst. 16(7): 816-829 (2008) | |
| 2006 | ||
| 25 | Soha Hassoun: 2006 International Conference on Computer-Aided Design (ICCAD'06), November 5-9, 2006, San Jose, CA, USA ACM 2006 | |
| 24 | Brian Swahn, Soha Hassoun: Gate sizing: finFETs vs 32nm bulk MOSFETs. DAC 2006: 528-531 | |
| 23 | Brian Swahn, Soha Hassoun: METS: A Metric for Electro-Thermal Sensitivity, and Its Application To FinFETs. ISQED 2006: 121-126 | |
| 2005 | ||
| 22 | Soha Hassoun, Murali Kudlugi, Duaine Pryor, Charles Selvidge: A transaction-based unified architecture for simulation and emulation. IEEE Trans. VLSI Syst. 13(2): 278-287 (2005) | |
| 2003 | ||
| 21 | Brian Swahn, Soha Hassoun: Hardware Scheduling for Dynamic Adaptability using External Profiling and Hardware Threading. ICCAD 2003: 58-65 | |
| 20 | Soha Hassoun: Optimal use of 2-phase transparent latches in buffered maze routing. ISCAS (4) 2003: 688-691 | |
| 19 | Soha Hassoun, Geert Janssen: First CADathlon Programming Contest held at 2002 ICCAD. IEEE Design & Test of Computers 20(3): 104-107 (2003) | |
| 18 | Sani R. Nassif, Soha Hassoun: Guest Editors' Introduction: On-Chip Power Distribution Networks. IEEE Design & Test of Computers 20(3): 5-6 (2003) | |
| 17 | Soha Hassoun, Yong-Bin Kim, Fabrizio Lombardi: Guest Editors' Introduction: Clockless VLSI Systems. IEEE Design & Test of Computers 20(6): 5-8 (2003) | |
| 16 | Soha Hassoun, Charles J. Alpert: Optimal path routing in single- and multiple-clock domain systems. IEEE Trans. on CAD of Integrated Circuits and Systems 22(11): 1580-1588 (2003) | |
| 15 | Soha Hassoun, Steven M. Nowick, Leon Stok: Guest Editorial. IEEE Trans. on CAD of Integrated Circuits and Systems 22(6): 662-664 (2003) | |
| 14 | Soha Hassoun, Christopher Cromer, Eduardo Calvillo-Gámez: Static timing analysis for level-clocked circuits in the presence of crosstalk. IEEE Trans. on CAD of Integrated Circuits and Systems 22(9): 1270-1277 (2003) | |
| 2002 | ||
| 13 | Soha Hassoun, Eduardo Calvillo-Gámez, Christopher Cromer: Verifying Clock Schedules in the Presence of Cross Talk. DATE 2002: 346-350 | |
| 12 | Soha Hassoun, Charles J. Alpert, Meera Thiagarajan: Optimal buffered routing path constructions for single and multiple clock domain systems. ICCAD 2002: 247-253 | |
| 11 | Fadi A. Aloul, Soha Hassoun, Karem A. Sakallah, David Blaauw: Robust SAT-Based Search Algorithm for Leakage Power Reduction. PATMOS 2002: 167-177 | |
| 2001 | ||
| 10 | Murali Kudlugi, Soha Hassoun, Charles Selvidge, Duaine Pryor: A Transaction-Based Unified Simulation/Emulation Architecture for Functional Verification. DAC 2001: 623-628 | |
| 9 | Soha Hassoun, Soheila Bana: Practices for Recruiting and Retaining Graduate Women Students in Computer Science and Engineering. MSE 2001: 106- | |
| 2000 | ||
| 8 | Soha Hassoun: Critical path analysis using a dynamically bounded delay model. DAC 2000: 260-265 | |
| 1999 | ||
| 7 | Soha Hassoun, Carolyn McCreary: Regularity extraction via clan-based structural circuit decomposition. ICCAD 1999: 414-419 | |
| 1998 | ||
| 6 | William J. Dally, Linda Chao, Andrew A. Chien, Soha Hassoun, Waldemar Horwat, Jon Kaplan, Paul Song, Brian Totty, D. Scott Wills: Architecture of a Message-Driven Processor. 25 Years ISCA: Retrospectives and Reprints 1998: 337-344 | |
| 5 | Soha Hassoun, Carl Ebeling: Using precomputation in architecture and logic resynthesis. ICCAD 1998: 316-323 | |
| 4 | Soha Hassoun: Fine Grain Incremental Rescheduling Via Architectural Retiming. ISSS 1998: 158-163 | |
| 1996 | ||
| 3 | Soha Hassoun, Carl Ebeling: Architectural Retiming: Pipelining Latency-Constrained Circuts. DAC 1996: 708-713 | |
| 1993 | ||
| 2 | Kevin Bolding, Sen-Ching Cheung, Sung-Eun Choi, Carl Ebeling, Soha Hassoun, Ton Anh Ngo, Robert Wille: The chaos router chip: design and implementation of an adaptive router. VLSI 1993: 311-320 | |
| 1987 | ||
| 1 | William J. Dally, Linda Chao, Andrew A. Chien, Soha Hassoun, Waldemar Horwat, Jon Kaplan, Paul Song, Brian Totty, D. Scott Wills: Architecture of a Message-Driven Processor. ISCA 1987: 189-196 | |
Colors in the list of coauthors
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