Masanori Hashimoto

	2012
96		Shuta Kimura, Masanori Hashimoto, Takao Onoye: Body bias clustering for low test-cost post-silicon tuning. ASP-DAC 2012: 283-289
95		Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye: Adaptive Performance Compensation With In-Situ Timing Error Predictive Sensors for Subthreshold Circuits. IEEE Trans. VLSI Syst. 20(2): 333-343 (2012)
	2011
94		Masanori Hashimoto: Run-time adaptive performance compensation using on-chip sensors. ASP-DAC 2011: 285-290
93		Kenichi Shinkai, Masanori Hashimoto: Device-parameter estimation with on-chip variation sensors considering random variability. ASP-DAC 2011: 683-688
92		Takehiko Amaki, Masanori Hashimoto, Takao Onoye: Jitter amplifier for oscillator-based true random number generator. ASP-DAC 2011: 81-82
91		Yasumichi Takai, Masanori Hashimoto, Takao Onoye: Power gating implementation for noise mitigation with body-tied triple-well structure. CICC 2011: 1-4
90		Hiroaki Konoura, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye: Implications of Reliability Enhancement Achieved by Fault Avoidance on Dynamically Reconfigurable Architectures. FPL 2011: 189-194
89		Takehiko Amaki, Masanori Hashimoto, Takao Onoye: An oscillator-based true random number generator with jitter amplifier. ISCAS 2011: 725-728
88		Toshihiro Kameda, Hiroaki Konoura, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye: NBTI Mitigation by Giving Random Scan-in Vectors during Standby Mode. PATMOS 2011: 152-161
87		Hiroshi Fuketa, Dan Kuroda, Masanori Hashimoto, Takao Onoye: An Average-Performance-Oriented Subthreshold Processor Self-Timed by Memory Read Completion. IEEE Trans. on Circuits and Systems 58-II(5): 299-303 (2011)
86		Takaaki Okumura, Masanori Hashimoto: Setup Time, Hold Time and Clock-to-Q Delay Computation under Dynamic Supply Noise. IEICE Transactions 94-A(10): 1948-1953 (2011)
85		Kenichi Shinkai, Masanori Hashimoto, Takao Onoye: Extracting Device-Parameter Variations with RO-Based Sensors. IEICE Transactions 94-A(12): 2537-2544 (2011)
84		Hiroaki Konoura, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye: Stress Probability Computation for Estimating NBTI-Induced Delay Degradation. IEICE Transactions 94-A(12): 2545-2553 (2011)
	2010
83		Shinya Abe, Kenichi Shinkai, Masanori Hashimoto, Takao Onoye: Clock skew reduction by self-compensating manufacturing variability with on-chip sensors. ACM Great Lakes Symposium on VLSI 2010: 197-202
82		Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye: Adaptive performance control with embedded timing error predictive sensors for subthreshold circuits. ASP-DAC 2010: 361-362
81		Takaaki Okumura, Fumihiro Minami, Kenji Shimazaki, Kimihiko Kuwada, Masanori Hashimoto: Gate delay estimation in STA under dynamic power supply noise. ASP-DAC 2010: 775-780
80		Takaaki Okumura, Masanori Hashimoto: Setup time, hold time and clock-to-Q delay computation under dynamic supply noise. CICC 2010: 1-4
79		Hiroaki Konoura, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye: Comparative study on delay degrading estimation due to NBTI with circuit/instance/transistor-level stress probability consideration. ISQED 2010: 646-651
78		Ryo Harada, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye: Measurement circuits for acquiring SET pulsewidth distribution with sub-FO1-inverter-delay resolution. ISQED 2010: 839-844
77		Takehiko Amaki, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye: A Design Procedure for Oscillator-Based Hardware Random Number Generator with Stochastic Behavior Modeling. WISA 2010: 107-121
76		Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye: Transistor Variability Modeling and its Validation With Ring-Oscillation Frequencies for Body-Biased Subthreshold Circuits. IEEE Trans. VLSI Syst. 18(7): 1118-1129 (2010)
75		Zhangcai Huang, Atsushi Kurokawa, Masanori Hashimoto, Takashi Sato, Minglu Jiang, Yasuaki Inoue: Modeling the Overshooting Effect for CMOS Inverter Delay Analysis in Nanometer Technologies. IEEE Trans. on CAD of Integrated Circuits and Systems 29(2): 250-260 (2010)
74		Takashi Enami, Shinyu Ninomiya, Kenichi Shinkai, Shinya Abe, Masanori Hashimoto: Statistical Timing Analysis Considering Clock Jitter and Skew due to Power Supply Noise and Process Variation. IEICE Transactions 93-A(12): 2399-2408 (2010)
73		Ryo Harada, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye: Measurement Circuits for Acquiring SET Pulse Width Distribution with Sub-FO1-Inverter-Delay Resolution. IEICE Transactions 93-A(12): 2417-2423 (2010)
72		Shinyu Ninomiya, Masanori Hashimoto: Accuracy Enhancement of Grid-Based SSTA by Coefficient Interpolation. IEICE Transactions 93-A(12): 2441-2446 (2010)
71		Takaaki Okumura, Fumihiro Minami, Kenji Shimazaki, Kimihiko Kuwada, Masanori Hashimoto: Gate Delay Estimation in STA under Dynamic Power Supply Noise. IEICE Transactions 93-A(12): 2447-2455 (2010)
70		Kenichi Shinkai, Masanori Hashimoto, Takao Onoye: Prediction of Self-Heating in Short Intra-Block Wires. IEICE Transactions 93-A(3): 583-594 (2010)
69		Toshiki Kanamoto, Takaaki Okumura, Katsuhiro Furukawa, Hiroshi Takafuji, Atsushi Kurokawa, Koutaro Hachiya, Tsuyoshi Sakata, Masakazu Tanaka, Hidenari Nakashima, Hiroo Masuda, Takashi Sato, Masanori Hashimoto: Impact of Self-Heating in Wire Interconnection on Timing. IEICE Transactions 93-C(3): 388-392 (2010)
	2009
68		Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye: Trade-off analysis between timing error rate and power dissipation for adaptive speed control with timing error prediction. ASP-DAC 2009: 266-271
67		Ling Zhang, Yulei Zhang, Akira Tsuchiya, Masanori Hashimoto, Ernest S. Kuh, Chung-Kuan Cheng: High performance on-chip differential signaling using passive compensation for global communication. ASP-DAC 2009: 385-390
66		Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye: Adaptive performance compensation with in-situ timing error prediction for subthreshold circuits. CICC 2009: 215-218
65		Dawood Alnajiar, Younghun Ko, Takashi Imagawa, Hiroaki Konoura, Masayuki Hiromoto, Yukio Mitsuyama, Masanori Hashimoto, Hiroyuki Ochi, Takao Onoye: Coarse-grained dynamically reconfigurable architecture with flexible reliability. FPL 2009: 186-192
64		Koichi Hamamoto, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye: Tuning-friendly body bias clustering for compensating random variability in subthreshold circuits. ISLPED 2009: 51-56
63		Shingo Watanabe, Masanori Hashimoto, Toshinori Sato: A case for exploiting complex arithmetic circuits towards performance yield enhancement. ISQED 2009: 401-407
62		Shinyu Ninomiya, Masanori Hashimoto: Enhancement of grid-based spatially-correlated variability modeling for improving SSTA accuracy. SoCC 2009: 337-340
61		Takashi Enami, Shinyu Ninomiya, Masanori Hashimoto: Statistical Timing Analysis Considering Spatially and Temporally Correlated Dynamic Power Supply Noise. IEEE Trans. on CAD of Integrated Circuits and Systems 28(4): 541-553 (2009)
60		Tsuyoshi Sakata, Takaaki Okumura, Atsushi Kurokawa, Hidenari Nakashima, Hiroo Masuda, Takashi Sato, Masanori Hashimoto, Koutaro Hachiya, Katsuhiro Furukawa, Masakazu Tanaka, Hiroshi Takafuji, Toshiki Kanamoto: An Approach for Reducing Leakage Current Variation due to Manufacturing Variability. IEICE Transactions 92-A(12): 3016-3023 (2009)
59		Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye: Trade-Off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction. IEICE Transactions 92-A(12): 3094-3102 (2009)
58		Takaaki Okumura, Atsushi Kurokawa, Hiroo Masuda, Toshiki Kanamoto, Masanori Hashimoto, Hiroshi Takafuji, Hidenari Nakashima, Nobuto Ono, Tsuyoshi Sakata, Takashi Sato: Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations. IEICE Transactions 92-A(4): 990-997 (2009)
57		Koichi Hamamoto, Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye: An Experimental Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed Controllability. IEICE Transactions 92-C(2): 281-285 (2009)
	2008
56		Koichi Hamamoto, Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye: Experimental study on body-biasing layout style-- negligible area overhead enables sufficient speed controllability --. ACM Great Lakes Symposium on VLSI 2008: 387-390
55		Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye: Dynamic supply noise measurement circuit composed of standard cells suitable for in-site SoC power integrity verification. ASP-DAC 2008: 107-108
54		Ling Zhang, Jianhua Liu, Haikun Zhu, Chung-Kuan Cheng, Masanori Hashimoto: High performance current-mode differential logic. ASP-DAC 2008: 720-725
53		Takashi Enami, Masanori Hashimoto, Takashi Sato: Decoupling capacitance allocation for timing with statistical noise model and timing analysis. ICCAD 2008: 420-425
52		Yulei Zhang, Ling Zhang, Akira Tsuchiya, Masanori Hashimoto, Chung-Kuan Cheng: On-chip high performance signaling using passive compensation. ICCD 2008: 182-187
51		Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye: Correlation verification between transistor variability model with body biasing and ring oscillation frequency in 90nm subthreshold circuits. ISLPED 2008: 3-8
50		Takashi Enami, Shinyu Ninomiya, Masanori Hashimoto: Statistical timing analysis considering spatially and temporally correlated dynamic power supply noise. ISPD 2008: 160-167
49		Shinya Abe, Masanori Hashimoto, Takao Onoye: Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution. ISQED 2008: 520-525
48		Toshiki Kanamoto, Yasuhiro Ogasahara, Keiko Natsume, Kenji Yamaguchi, Hiroyuki Amishiro, Tetsuya Watanabe, Masanori Hashimoto: Impact of Well Edge Proximity Effect on Timing. IEICE Transactions 91-A(12): 3461-3464 (2008)
47		Masanori Hashimoto, Jangsombatsiri Siriporn, Akira Tsuchiya, Haikun Zhu, Chung-Kuan Cheng: Analytical Eye-Diagram Model for On-Chip Distortionless Transmission Lines and Its Application to Design Space Exploration. IEICE Transactions 91-A(12): 3474-3480 (2008)
46		Shinya Abe, Masanori Hashimoto, Takao Onoye: Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution. IEICE Transactions 91-A(12): 3481-3487 (2008)
45		Yukio Mitsuyama, Kazuma Takahashi, Rintaro Imai, Masanori Hashimoto, Takao Onoye, Isao Shirakawa: Area-Efficient Reconfigurable Architecture for Media Processing. IEICE Transactions 91-A(12): 3651-3662 (2008)
44		Masanori Hashimoto, Junji Yamaguchi, Takashi Sato, Hidetoshi Onodera: Timing Analysis Considering Temporal Supply Voltage Fluctuation. IEICE Transactions 91-D(3): 655-660 (2008)
	2007
43		Kenichi Shinkai, Masanori Hashimoto, Takao Onoye: Future Prediction of Self-Heating in Short Intra-Block Wires. ISQED 2007: 660-665
42		Masanori Hashimoto, Junji Yamaguchi, Hidetoshi Onodera: Timing Analysis Considering Spatial Power/Ground Level Variation. IEICE Transactions 90-A(12): 2661-2668 (2007)
41		Masanori Hashimoto, Takahito Ijichi, Shingo Takahashi, Shuji Tsukiyama, Isao Shirakawa: Transistor Sizing of LCD Driver Circuit for Technology Migration. IEICE Transactions 90-A(12): 2712-2717 (2007)
40		Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye: Quantitative Prediction of On-Chip Capacitive and Inductive Crosstalk Noise and Tradeoff between Wire Cross-Sectional Area and Inductive Crosstalk Effect. IEICE Transactions 90-A(4): 724-731 (2007)
39		Hiroyuki Kobayashi, Nobuto Ono, Takashi Sato, Jiro Iwai, Hidenari Nakashima, Takaaki Okumura, Masanori Hashimoto: Proposal of Metrics for SSTA Accuracy Evaluation. IEICE Transactions 90-A(4): 808-814 (2007)
38		Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera: Optimal Termination of On-Chip Transmission-Lines for High-Speed Signaling. IEICE Transactions 90-C(6): 1267-1273 (2007)
	2006
37		Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera: Interconnect RL extraction at a single representative frequency. ASP-DAC 2006: 515-520
36		Kenichi Shinkai, Masanori Hashimoto, Atsushi Kurokawa, Takao Onoye: A gate delay model focusing on current fluctuation over wide-range of process and environmental variability. ICCAD 2006: 47-53
35		Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye: Quantitative Prediction of On-chip Capacitive and Inductive Crosstalk Noise and Discussion on Wire Cross-Sectional Area Toward Inductive Crosstalk Free Interconnects. ICCD 2006
34		Takashi Sato, Junji Ichimiya, Nobuto Ono, Masanori Hashimoto: On-Chip Thermal Gradient Analysis Considering Interdependence between Leakage Power and Temperature. IEICE Transactions 89-A(12): 3491-3499 (2006)
33		Shingo Takahashi, Shuji Tsukiyama, Masanori Hashimoto, Isao Shirakawa: A Sampling Switch Design Procedure for Active Matrix Liquid Crystal Displays. IEICE Transactions 89-A(12): 3538-3545 (2006)
32		Toshiki Kanamoto, Tatsuhiko Ikeda, Akira Tsuchiya, Hidetoshi Onodera, Masanori Hashimoto: Si-Substrate Modeling toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design. IEICE Transactions 89-A(12): 3560-3568 (2006)
31		Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera: Interconnect RL Extraction Based on Transfer Characteristics of Transmission-Line. IEICE Transactions 89-A(12): 3585-3593 (2006)
30		Toshiki Kanamoto, Shigekiyo Akutsu, Tamiyo Nakabayashi, Takahiro Ichinomiya, Koutaro Hachiya, Atsushi Kurokawa, Hiroshi Ishikawa, Sakae Muromoto, Hiroyuki Kobayashi, Masanori Hashimoto: Impact of Intrinsic Parasitic Extraction Errors on Timing and Noise Estimation. IEICE Transactions 89-A(12): 3666-3670 (2006)
	2005
29		Yoshihiro Uchida, Sadahiro Tani, Masanori Hashimoto, Shuji Tsukiyama, Isao Shirakawa: Interconnect capacitance extraction for system LCD circuits. ACM Great Lakes Symposium on VLSI 2005: 160-163
28		Takashi Sato, Junji Ichimiya, Nobuto Ono, Koutaro Hachiya, Masanori Hashimoto: On-chip thermal gradient analysis and temperature flattening for SoC design. ASP-DAC 2005: 1074-1077
27		Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera: Return path selection for loop RL extraction. ASP-DAC 2005: 1078-1081
26		Masanori Hashimoto, Junji Yamaguchi, Takashi Sato, Hidetoshi Onodera: Timing analysis considering temporal supply voltage fluctuation. ASP-DAC 2005: 1098-1101
25		Takashi Sato, Masanori Hashimoto, Hidetoshi Onodera: Successive pad assignment algorithm to optimize number and location of power supply pad using incremental matrix inversion. ASP-DAC 2005: 723-728
24		Akinori Shinmyo, Masanori Hashimoto, Hidetoshi Onodera: Design and measurement of 6.4 Gbps 8: 1 multiplexer in 0.18µm CMOS process. ASP-DAC 2005: 9-10
23		Atsushi Muramatsu, Masanori Hashimoto, Hidetoshi Onodera: Effects of on-chip inductance on power distribution grid. ISPD 2005: 63-69
22		Masanori Hashimoto, Tomonori Yamamoto, Hidetoshi Onodera: Statistical Analysis of Clock Skew Variation in H-Tree Structure. ISQED 2005: 402-407
21		Masanori Hashimoto, Tomonori Yamamoto, Hidetoshi Onodera: Statistical Analysis of Clock Skew Variation in H-Tree Structure. IEICE Transactions 88-A(12): 3375-3381 (2005)
20		Takashi Sato, Junji Ichimiya, Nobuto Ono, Koutaro Hachiya, Masanori Hashimoto: On-Chip Thermal Gradient Analysis and Temperature Flattening for SoC Design. IEICE Transactions 88-A(12): 3382-3389 (2005)
19		Takashi Sato, Masanori Hashimoto, Hidetoshi Onodera: Successive Pad Assignment for Minimizing Supply Voltage Drop. IEICE Transactions 88-A(12): 3429-3436 (2005)
18		Atsushi Kurokawa, Masanori Hashimoto, Akira Kasebe, Zhangcai Huang, Yun Yang, Yasuaki Inoue, Ryosuke Inagaki, Hiroo Masuda: Second-Order Polynomial Expressions for On-Chip Interconnect Capacitance. IEICE Transactions 88-A(12): 3453-3462 (2005)
17		Atsushi Muramatsu, Masanori Hashimoto, Hidetoshi Onodera: Effects of On-Chip Inductance on Power Distribution Grid. IEICE Transactions 88-A(12): 3564-3572 (2005)
16		Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera: Performance Limitation of On-Chip Global Interconnects for High-Speed Signaling. IEICE Transactions 88-A(4): 885-891 (2005)
15		Takahito Miyazaki, Masanori Hashimoto, Hidetoshi Onodera: A Performance Prediction of Clock Generation PLLs: A Ring Oscillator Based PLL and an LC Oscillator Based PLL. IEICE Transactions 88-C(3): 437-444 (2005)
	2004
14		Takahito Miyazaki, Masanori Hashimoto, Hidetoshi Onodera: A performance comparison of PLLs for clock generation using ring oscillator VCO and LC oscillator in a digital CMOS process. ASP-DAC 2004: 545-546
13		Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera: Representative frequency for interconnect R(f)L(f)C extraction. ASP-DAC 2004: 691-696
12		Masanori Hashimoto, Junji Yamaguchi, Hidetoshi Onodera: Timing analysis considering spatial power/ground level variation. ICCAD 2004: 814-820
11		Masanori Hashimoto, Kazunori Fujimori, Hidetoshi Onodera: Automatic Generation of Standard Cell Library in VDSM Technologies. ISQED 2004: 36-41
10		Masanori Hashimoto, Yuji Yamada, Hidetoshi Onodera: Equivalent waveform propagation for static timing analysis. IEEE Trans. on CAD of Integrated Circuits and Systems 23(4): 498-508 (2004)
	2003
9		Masanori Hashimoto, Yuji Yamada, Hidetoshi Onodera: Equivalent Waveform Propagation for Static Timing Analysis. ICCAD 2003: 169-175
8		Masanori Hashimoto, Yuji Yamada, Hidetoshi Onodera: Capturing crosstalk-induced waveform for accurate static timing analysis. ISPD 2003: 18-23
	2002
7		Masanori Hashimoto, Masao Takahashi, Hidetoshi Onodera: Crosstalk noise optimization by post-layout transistor sizing. ISPD 2002: 126-130
6		Masanori Hashimoto, Yashiteru Hayashi, Hidetoshi Onodera: Experimental Study on Cell-Base High-Performance Datapath Design. IWLS 2002: 283-287
	2001
5		Masanori Hashimoto, Hidetoshi Onodera: Post-layout transistor sizing for power reduction in cell-based design. ASP-DAC 2001: 359-365
4		Masao Takahashi, Masanori Hashimoto, Hidetoshi Onodera: Crosstalk Noise Estimation for Generic RC Trees. ICCD 2001: 110-117
	2000
3		Masanori Hashimoto, Hidetoshi Onodera: A performance optimization method by gate sizing using statistical static timing analysis. ISPD 2000: 111-116
	1999
2		Masanori Hashimoto, Hidetoshi Onodera, Keikichi Tamaru: A Practical Gate Resizing Technique Considering Glitch Reduction for Low Power Design. DAC 1999: 446-451
	1998
1		Masanori Hashimoto, Hidetoshi Onodera, Keikichi Tamaru: A power optimization method considering glitch reduction by gate sizing. ISLPED 1998: 221-226

Coauthor Index

1	Shinya Abe	[46] [49] [74] [83]
2	Shigekiyo Akutsu	[30]
3	Dawood Alnajiar	[65]
4	Takehiko Amaki	[77] [89] [92]
5	Hiroyuki Amishiro	[48]
6	Chung-Kuan Cheng	[47] [52] [54] [67]
7	Takashi Enami	[50] [53] [61] [74]
8	Kazunori Fujimori	[11]
9	Hiroshi Fuketa	[51] [56] [57] [59] [66] [68] [76] [82] [87] [95]
10	Katsuhiro Furukawa	[60] [69]
11	Koutaro Hachiya	[20] [28] [30] [60] [69]
12	Koichi Hamamoto	[56] [57] [64]
13	Ryo Harada	[73] [78]
14	Yashiteru Hayashi	[6]
15	Masayuki Hiromoto	[65]
16	Zhangcai Huang	[18] [75]
17	Junji Ichimiya	[20] [28] [34]
18	Takahiro Ichinomiya	[30]
19	Takahito Ijichi	[41]
20	Tatsuhiko Ikeda	[32]
21	Takashi Imagawa	[65]
22	Rintaro Imai	[45]
23	Ryosuke Inagaki	[18]
24	Yasuaki Inoue	[18] [75]
25	Hiroshi Ishikawa	[30]
26	Jiro Iwai	[39]
27	Minglu Jiang	[75]
28	Toshihiro Kameda	[88]
29	Toshiki Kanamoto	[30] [32] [48] [58] [60] [69]
30	Akira Kasebe	[18]
31	Shuta Kimura	[96]
32	Younghun Ko	[65]
33	Hiroyuki Kobayashi	[30] [39]
34	Hiroaki Konoura	[65] [79] [84] [88] [90]
35	Ernest S. Kuh	[67]
36	Dan Kuroda	[87]
37	Atsushi Kurokawa	[18] [30] [36] [58] [60] [69] [75]
38	Kimihiko Kuwada	[71] [81]
39	Jianhua Liu	[54]
40	Hiroo Masuda	[18] [58] [60] [69]
41	Fumihiro Minami	[71] [81]
42	Yukio Mitsuyama	[45] [51] [56] [57] [59] [64] [65] [66] [68] [73] [76] [77] [78] [79] [82] [84] [88] [90] [95]
43	Takahito Miyazaki	[14] [15]
44	Atsushi Muramatsu	[17] [23]
45	Sakae Muromoto	[30]
46	Tamiyo Nakabayashi	[30]
47	Hidenari Nakashima	[39] [58] [60] [69]
48	Keiko Natsume	[48]
49	Shinyu Ninomiya	[50] [61] [62] [72] [74]
50	Hiroyuki Ochi	[65]
51	Yasuhiro Ogasahara	[35] [40] [48] [55]
52	Takaaki Okumura	[39] [58] [60] [69] [71] [80] [81] [86]
53	Nobuto Ono	[20] [28] [34] [39] [58]
54	Hidetoshi Onodera	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [19] [21] [22] [23] [24] [25] [26] [27] [31] [32] [37] [38] [42] [44]
55	Takao Onoye	[35] [36] [40] [43] [45] [46] [49] [51] [55] [56] [57] [59] [64] [65] [66] [68] [70] [73] [76] [77] [78] [79] [82] [83] [84] [85] [87] [88] [89] [90] [91] [92] [95] [96]
56	Tsuyoshi Sakata	[58] [60] [69]
57	Takashi Sato	[19] [20] [25] [26] [28] [34] [39] [44] [53] [58] [60] [69] [75]
58	Toshinori Sato	[63]
59	Kenji Shimazaki	[71] [81]
60	Kenichi Shinkai	[36] [43] [70] [74] [83] [85] [93]
61	Akinori Shinmyo	[24]
62	Isao Shirakawa	[29] [33] [41] [45]
63	Jangsombatsiri Siriporn	[47]
64	Hiroshi Takafuji	[58] [60] [69]
65	Kazuma Takahashi	[45]
66	Masao Takahashi	[4] [7]
67	Shingo Takahashi	[33] [41]
68	Yasumichi Takai	[91]
69	Keikichi Tamaru	[1] [2]
70	Masakazu Tanaka	[60] [69]
71	Sadahiro Tani	[29]
72	Akira Tsuchiya	[13] [16] [27] [31] [32] [37] [38] [47] [52] [67]
73	Shuji Tsukiyama	[29] [33] [41]
74	Yoshihiro Uchida	[29]
75	Shingo Watanabe	[63]
76	Tetsuya Watanabe	[48]
77	Yuji Yamada	[8] [9] [10]
78	Junji Yamaguchi	[12] [26] [42] [44]
79	Kenji Yamaguchi	[48]
80	Tomonori Yamamoto	[21] [22]
81	Yun Yang	[18]
82	Ling Zhang	[52] [54] [67]
83	Yulei Zhang	[52] [67]
84	Haikun Zhu	[47] [54]

Colors in the list of coauthors

Last update Thu May 31 18:55:10 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page