Yohei Hasegawa

	2009
20		Lei Zhao, Hui Xu, Naomi Seki, Yoshiki Saito, Yohei Hasegawa, Kimiyoshi Usami, Hideharu Amano: Cache Controller Design on Ultra Low Leakage Embedded Processors. ARCS 2009: 171-182
19		Shotaro Saito, Yoshinori Kohama, Yasufumi Sugimori, Yohei Hasegawa, Hiroki Matsutani, Toru Sano, Kazutaka Kasuga, Yoichi Yoshida, Kiichi Niitsu, Noriyuki Miura, Tadahiro Kuroda, Hideharu Amano: MuCCRA-Cube: A 3D dynamically reconfigurable processor with inductive-coupling link. FPL 2009: 6-11
18		Yohei Hasegawa, Masahiro Jibiki: Ethernet Topology Detection from a Single Host without Assistance of Network Nodes or Other Hosts. IEICE Transactions 92-B(4): 1128-1136 (2009)
	2008
17		Masaru Kato, Yohei Hasegawa, Hideharu Amano: Evaluation of MuCCRA-D: A Dynamically Reconfigurable Processor with Directly Interconnected PEs. ERSA 2008: 215-221
16		Toru Sano, Masaru Kato, Satoshi Tsutsumi, Yohei Hasegawa, Hideharu Amano: Instruction buffer mode for multi-context Dynamically Reconfigurable Processors. FPL 2008: 215-220
15		Takashi Nishimura, Keiichiro Hirai, Yoshiki Saito, Takuro Nakamura, Yohei Hasegawa, Satoshi Tsutsusmi, Vasutan Tunbunheng, Hideharu Amano: Power reduction techniques for Dynamically Reconfigurable Processor Arrays. FPL 2008: 305-310
14		Naomi Seki, Lei Zhao, Jo Kei, Daisuke Ikebuchi, Yu Kojima, Yohei Hasegawa, Hideharu Amano, Toshihiro Kashima, Seidai Takeda, Toshiaki Shirai, Mitsutaka Nakata, Kimiyoshi Usami, Tetsuya Sunata, Jun Kanai, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura: A fine-grain dynamic sleep control scheme in MIPS R3000. ICCD 2008: 612-617
	2007
13		Vu Manh Tuan, Yohei Hasegawa, Hideharu Amano: Performance Analysis of Multi-process Execution Model on Dynamically Reconfigurable Processor. ERSA 2007: 203-206
12		Yohei Hasegawa, Hideharu Amano: Design Methodology and Trade-offs Analysis for Parameterized Dynamically Reconfigurable Processor Arrays. FPL 2007: 796-799
11		Yohei Hasegawa, Ichiro Yamaguchi, Takayuki Hama, Hideyuki Shimonishi, Tutomu Murase: Deployable multipath communication scheme with sufficient performance data distribution method. Computer Communications 30(17): 3285-3292 (2007)
	2006
10		Vu Manh Tuan, Yohei Hasegawa, Naohiro Katsura, Hideharu Amano: Performance/Cost Trade-Off Evaluation for the DCT Implementation on the Dynamically Reconfigurable Processor. ARC 2006: 115-121
9		Hideharu Amano, Yohei Hasegawa, Shohei Abe, K. Ishikawa, Shunsuke Tsutsumi, Shunsuke Kurotaki, Takuro Nakamura, Takashi Nishimura: A Context Dependent Clock Control Mechanism for Dynamically Reconfigurable Processors. FPL 2006: 1-6
8		Masayasu Suzuki, Yohei Hasegawa, Vu Manh Tuan, Shohei Abe, Hideharu Amano: A cost-effective context memory structure for dynamically reconfigurable processors. IPDPS 2006
7		Yohei Hasegawa, Shohei Abe, Shunsuke Kurotaki, Vu Manh Tuan, Naohiro Katsura, Takuro Nakamura, Takashi Nishimura, Hideharu Amano: Performance and power analysis of time-multiplexed execution on dynamically reconfigurable processor. IPDPS 2006
	2005
6		Hideharu Amano, Shohei Abe, Yohei Hasegawa, Katsuaki Deguchi, Masayasu Suzuki: Performance and Cost Analysis of Time-Multiplexed Execution on the Dynamically Reconfigurable Processor. FCCM 2005: 315-316
5		Yohei Hasegawa, Shohei Abe, Katsuaki Deguchi, Masayasu Suzuki, Hideharu Amano: Time-multiplexed execution on the dynamically reconfigurable processor: a performance/cost evaluation. FPGA 2005: 265
4		Hideharu Amano, Shohei Abe, Katsuaki Deguchi, Yohei Hasegawa: An I/O mechanism on a Dynamically Reconfigurable Processor - Which should be moved: Data or Configuration? FPL 2005: 347-352
3		Yohei Hasegawa, Shohei Abe, Hiroki Matsutani, Hideharu Amano, Kenichiro Anjo, Toru Awashima: An Adaptive Cryptographic Accelerator for IPsec on Dynamically Reconfigurable Processor. FPT 2005: 163-170
	2004
2		Noriaki Suzuki, Shunsuke Kurotaki, Masayasu Suzuki, Naoto Kaneko, Yutaka Yamada, Katsuaki Deguchi, Yohei Hasegawa, Hideharu Amano, Kenichiro Anjo, Masato Motomura, Kazutoshi Wakabayashi, Takeo Toi, Toru Awashima: Implementing and Evaluating Stream Applications on the Dynamically Reconfigurable Processor. FCCM 2004: 328-329
	2001
1		Takashi Egawa, Koji Hino, Yohei Hasegawa: Fast and Secure Packet Processing Environment for Per-Packet QoS Customization. IWAN 2001: 34-48

Coauthor Index

1	Shohei Abe	[3] [4] [5] [6] [7] [8] [9]
2	Hideharu Amano	[2] [3] [4] [5] [6] [7] [8] [9] [10] [12] [13] [14] [15] [16] [17] [19] [20]
3	Kenichiro Anjo	[2] [3]
4	Toru Awashima	[2] [3]
5	Katsuaki Deguchi	[2] [4] [5] [6]
6	Takashi Egawa	[1]
7	Takayuki Hama	[11]
8	Koji Hino	[1]
9	Keiichiro Hirai	[15]
10	Daisuke Ikebuchi	[14]
11	K. Ishikawa	[9]
12	Masahiro Jibiki	[18]
13	Jun Kanai	[14]
14	Naoto Kaneko	[2]
15	Toshihiro Kashima	[14]
16	Kazutaka Kasuga	[19]
17	Masaru Kato	[16] [17]
18	Naohiro Katsura	[7] [10]
19	Jo Kei	[14]
20	Yoshinori Kohama	[19]
21	Yu Kojima	[14]
22	Masaaki Kondo	[14]
23	Tadahiro Kuroda	[19]
24	Shunsuke Kurotaki	[2] [7] [9]
25	Hiroki Matsutani	[3] [19]
26	Noriyuki Miura	[19]
27	Masato Motomura	[2]
28	Tutomu Murase	[11]
29	Hiroshi Nakamura	[14]
30	Takuro Nakamura	[7] [9] [15]
31	Mitsutaka Nakata	[14]
32	Mitaro Namiki	[14]
33	Kiichi Niitsu	[19]
34	Takashi Nishimura	[7] [9] [15]
35	Shotaro Saito	[19]
36	Yoshiki Saito	[15] [20]
37	Toru Sano	[16] [19]
38	Naomi Seki	[14] [20]
39	Hideyuki Shimonishi	[11]
40	Toshiaki Shirai	[14]
41	Yasufumi Sugimori	[19]
42	Tetsuya Sunata	[14]
43	Masayasu Suzuki	[2] [5] [6] [8]
44	Noriaki Suzuki	[2]
45	Seidai Takeda	[14]
46	Takeo Toi	[2]
47	Satoshi Tsutsumi	[16]
48	Shunsuke Tsutsumi	[9]
49	Satoshi Tsutsusmi	[15]
50	Vu Manh Tuan	[7] [8] [10] [13]
51	Vasutan Tunbunheng	[15]
52	Kimiyoshi Usami	[14] [20]
53	Kazutoshi Wakabayashi	[2]
54	Hui Xu	[20]
55	Yutaka Yamada	[2]
56	Ichiro Yamaguchi	[11]
57	Yoichi Yoshida	[19]
58	Lei Zhao	[14] [20]

Colors in the list of coauthors

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