Mohd. Hasan

	2012
14		S. D. Pable, Mohd. Hasan: Ultra-low-power signaling challenges for subthreshold global interconnects. Integration 45(2): 186-196 (2012)
13		Aminul Islam, Mohd. Hasan: A technique to mitigate impact of process, voltage and temperature variations on design metrics of SRAM Cell. Microelectronics Reliability 52(2): 405-411 (2012)
	2011
12		S. D. Pable, Mohd. Hasan: Performance analysis of FPGA interconnect fabric for ultra-low power applications. ICCCS 2011: 210-214
11		S. D. Pable, Mohd. Hasan: Performance optimization of CNFET for ultra-low power reconfigurable architecture. ICCCS 2011: 215-220
10		S. D. Pable, Mohd. Hasan: High speed interconnect through device optimization for subthreshold FPGA. Microelectronics Journal 42(3): 545-552 (2011)
	2010
9		Aminul Islam, Mohd. Hasan: High Speed Cache Design Using Multi-diameter CNFET at 32nm Technology. ICT 2010: 215-222
	2009
8		Mohd. Hasan, A. K. Kureshi, Tughrul Arslan: Leakage Reduction in FPGA Routing Multiplexers. ISCAS 2009: 1129-1132
7		Naushad Alam, A. K. Kureshi, Mohd. Hasan, Tughrul Arslan: Carbon Nanotube Interconnects for Low-power High-speed Applications. ISCAS 2009: 2273-2276
6		A. K. Kureshi, Naushad Alam, Mohd. Hasan, Tughrul Arslan: Subthreshold Deep Submicron Performance Investigation of CMOS and DTCMOS Biasing Schemes for Reconfigurable Computing. ISCAS 2009: 2545-2548
5		A. K. Kureshi, Mohd. Hasan: Performance comparison of CNFET- and CMOS-based 6T SRAM cell in deep submicron. Microelectronics Journal 40(6): 979-982 (2009)
	2005
4		Wei Han, Ahmet T. Erdogan, Tughrul Arslan, Mohd. Hasan: The development of high performance FFT IP cores through hybrid low power algorithmic methodology. ASP-DAC 2005: 549-552
3		Wei Han, Ahmet T. Erdogan, Tughrul Arslan, Mohd. Hasan: Low power commutator for pipelined FFT processors. ISCAS (5) 2005: 5274-5277
	2003
2		Mohd. Hasan, Tughrul Arslan: A triple port RAM based low power commutator architecture for a pipelined FFT processor. ISCAS (5) 2003: 353-356
	2002
1		Mohd. Hasan, Tughrul Arslan: A coefficient memory addressing scheme for VLSI implementation of FFT processors. ISCAS (4) 2002: 850-853

Coauthor Index

1	Naushad Alam	[6] [7]
2	Tughrul Arslan	[1] [2] [3] [4] [6] [7] [8]
3	Ahmet T. Erdogan	[3] [4]
4	Wei Han	[3] [4]
5	Aminul Islam	[9] [13]
6	A. K. Kureshi	[5] [6] [7] [8]
7	S. D. Pable	[10] [11] [12] [14]

Colors in the list of coauthors

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