Baher Haroun

	2012
15		Venkatesh Srinivasan, Victoria Wang, Patrick Satarzadeh, Baher Haroun, Marco Corsi: A 20mW 61dB SNDR (60MHz BW) 1b 3rd-order continuous-time delta-sigma modulator clocked at 6GHz in 45nm CMOS. ISSCC 2012: 158-160
14		Baher Haroun, Gyu-Hyeong Cho: Session 16 overview: Switching power control techniques: Analog subcommittee. ISSCC 2012: 272-273
	2010
13		Yogesh K. Ramadass, Ayman A. Fayed, Baher Haroun, Anantha Chandrakasan: A 0.16mm2 completely on-chip switched-capacitor DC-DC converter using digital capacitance modulation for LDO replacement in 45nm CMOS. ISSCC 2010: 208-209
12		Rahmi Hezar, Lars Risbo, Halil Kiper, Mounir Fares, Baher Haroun, G. Burra, Gabriel Gomez: A 110dB SNR and 0.5mW current-steering audio DAC implemented in 45nm CMOS. ISSCC 2010: 304-305
	2006
11		Jinseok Koh, Gabriel Gomez, Khurram Muhammad, Robert B. Staszewski, Baher Haroun: A Sigma-Delta ADC with Decimation and Gain Control Function for a Bluetooth Receiver in 130 nm Digital CMOS. EURASIP J. Wireless Comm. and Networking 2006: (2006)
	2002
10		Prasun Raha, Scott Randall, Richard Jennings, Bob Helmick, Ajith Amerasekera, Baher Haroun: A Robust Digital Delay Line Architecture in a 0.13µm CMOS Technology Node for Reduced Design and Process Sensitivities. ISQED 2002: 148-
	1995
9		Baher Haroun, Behzad Sajjadi: Synthesis of Signal Processing Structured Datapaths for FPGAs Supporting RAMs and Busses. FPGA 1995: 75-81
8		Abdelhakim Safir, Baher Haroun, Krishnaiyan Thulasiraman: Floorplanning with Datapath Optimization. ISCAS 1995: 41-44
	1994
7		Baher Haroun, Behzard Sajjadi: Optimal Datapath Synthesis of Partitioned Signal Processing Algorithm for Multiple FPGAs. ICCD 1994: 587-589
6		Abdelhakim Safir, Baher Haroun, Krishnaiyan Thulasiraman: A Floorplanner driven by Structural & Timing Constraints. ISCAS 1994: 157-160
5		Reza Golshan, Baher Haroun: A Novel Reduced Swing CMOS Bus Interface Circuit for High Speed Low Power VLSI Systems. ISCAS 1994: 351-354
4		Baher Haroun, Chao Hua Wu: A Two Stage Structure for High Order Multi-Bit Sigma-Delta ADC with Multiplier-less Digital Correction Logic. ISCAS 1994: 9-12
	1992
3		F. Rouatbi, Baher Haroun, Asim J. Al-Khalili: Power estimation tool for sub-micron CMOS VLSI circuits. ICCAD 1992: 204-209
2		Baher Haroun, Elie Torbey: Synthesis of Multiple Bus/Functional Unit Architectures Implementing Neural Networks. ICCD 1992: 174-178
	1989
1		Baher Haroun, Mohamed I. Elmasry: Architectural synthesis for DSP silicon compilers. IEEE Trans. on CAD of Integrated Circuits and Systems 8(4): 431-447 (1989)

Coauthor Index

1	Asim J. Al-Khalili (A. J. Al-Khalili)	[3]
2	Ajith Amerasekera	[10]
3	G. Burra	[12]
4	Anantha Chandrakasan (Anantha P. Chandrakasan)	[13]
5	Gyu-Hyeong Cho	[14]
6	Marco Corsi	[15]
7	Mohamed I. Elmasry	[1]
8	Mounir Fares	[12]
9	Ayman A. Fayed	[13]
10	Reza Golshan	[5]
11	Gabriel Gomez	[11] [12]
12	Bob Helmick	[10]
13	Rahmi Hezar	[12]
14	Richard Jennings	[10]
15	Halil Kiper	[12]
16	Jinseok Koh	[11]
17	Khurram Muhammad	[11]
18	Prasun Raha	[10]
19	Yogesh K. Ramadass	[13]
20	Scott Randall	[10]
21	Lars Risbo	[12]
22	F. Rouatbi	[3]
23	Abdelhakim Safir	[6] [8]
24	Behzad Sajjadi	[9]
25	Behzard Sajjadi	[7]
26	Patrick Satarzadeh	[15]
27	Venkatesh Srinivasan	[15]
28	Robert B. Staszewski (Robert Bogdan Staszewski)	[11]
29	Krishnaiyan Thulasiraman	[6] [8]
30	Elie Torbey	[2]
31	Victoria Wang	[15]
32	Chao Hua Wu	[4]

Colors in the list of coauthors

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