B. P. Harish

	2009
4		B. P. Harish, Navakanta Bhat, Mahesh B. Patil: Bridging Technology-CAD and Design-CAD for Variability Aware Nano-CMOS Circuits. ISCAS 2009: 2309-2312
	2008
3		B. P. Harish, Navakanta Bhat, Mahesh B. Patil: Hybrid-CV Modeling for Estimating the Variability in Dynamic Power. J. Low Power Electronics 4(3): 263-274 (2008)
	2007
2		B. P. Harish, Navakanta Bhat, Mahesh B. Patil: Process Variability-Aware Statistical Hybrid Modeling of Dynamic Power Dissipation in 65 nm CMOS Designs. ICCTA 2007: 94-98
1		B. P. Harish, Navakanta Bhat, Mahesh B. Patil: On a Generalized Framework for Modeling the Effects of Process Variations on Circuit Delay Performance Using Response Surface Methodology. IEEE Trans. on CAD of Integrated Circuits and Systems 26(3): 606-614 (2007)

Coauthor Index

1	Navakanta Bhat	[1] [2] [3] [4]
2	Mahesh B. Patil	[1] [2] [3] [4]

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