R. Harinath

	2000
2		Allalaghatta Pavan, Vipin Gopal, S. Song, N. Birch, R. Harinath, D. Castanon: Admission control and resource allocation in a strictly priority based network. RTCSA 2000: 231-
1		B. Suresh, Biswadeep Chaterjee, R. Harinath: Synthesizable RAM-Alternative to Low Configuration Compiler Memory for Die Area Reduction. VLSI Design 2000: 512-517

Coauthor Index

1	N. Birch	[2]
2	D. Castanon	[2]
3	Biswadeep Chaterjee	[1]
4	Vipin Gopal	[2]
5	Allalaghatta Pavan	[2]
6	S. Song	[2]
7	B. Suresh	[1]

Colors in the list of coauthors

Last update Fri Jun 1 15:44:53 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page