 | 2012 |
| 7 |  | Siva Kumar Sastry Hari,
Sarita V. Adve,
Helia Naeimi,
Pradeep Ramachandran:
Relyzer: exploiting application-level fault equivalence to analyze application resiliency to transient faults.
ASPLOS 2012: 123-134 |
| 6 |  | Andrea Pellegrini,
Robert Smolinski,
Lei Chen,
Xin Fu,
Siva Kumar Sastry Hari,
Junhao Jiang,
Sarita V. Adve,
Todd M. Austin,
Valeria Bertacco:
CrashTest'ing SWAT: Accurate, gate-level evaluation of symptom-based resiliency solutions.
DATE 2012: 1106-1109 |
| 2011 |
| 5 |  | Dimitris Gizopoulos,
Mihalis Psarakis,
Sarita V. Adve,
Pradeep Ramachandran,
Siva Kumar Sastry Hari,
Daniel J. Sorin,
Albert Meixner,
A. Biswas,
Xavier Vera:
Architectures for online error detection and recovery in multicore processors.
DATE 2011: 533-538 |
| 2009 |
| 4 |  | Man-Lap Li,
Pradeep Ramachandran,
Ulya R. Karpuzcu,
Siva Kumar Sastry Hari,
Sarita V. Adve:
Accurate microarchitecture-level fault modeling for studying hardware faults.
HPCA 2009: 105-116 |
| 3 |  | Siva Kumar Sastry Hari,
Man-Lap Li,
Pradeep Ramachandran,
Byn Choi,
Sarita V. Adve:
mSWAT: low-cost hardware fault detection and diagnosis for multicore systems.
MICRO 2009: 122-132 |
| 2008 |
| 2 |  | Siva Kumar Sastry Hari,
Vishnu Vardhan Reddy Konda,
V. Kamakoti,
Vivekananda M. Vedula,
K. S. Maneperambil:
Automatic Constraint Based Test Generation for Behavioral HDL Models.
IEEE Trans. VLSI Syst. 16(4): 408-421 (2008) |
| 2007 |
| 1 |  | K. Najeeb,
Vishnu Vardhan Reddy Konda,
Siva Kumar Sastry Hari,
V. Kamakoti,
Vivekananda M. Vedula:
Power Virus Generation Using Behavioral Models of Circuits.
VTS 2007: 35-42 |