Erich F. Haratsch

	2012
8		Yu Cai, Erich F. Haratsch, Onur Mutlu, Ken Mai: Error patterns in MLC NAND flash memory: Measurement, characterization, and analysis. DATE 2012: 521-526
	2011
7		Yu Cai, Erich F. Haratsch, Mark McCartney, Ken Mai: FPGA-Based Solid-State Drive Prototyping Platform. FCCM 2011: 101-104
6		Yu Cai, Erich F. Haratsch, Mark McCartney, Mudit Bhargava, Ken Mai: FPGA-based nand flash memory error characterization and solid-state drive prototyping platform (abstract only). FPGA 2011: 284
	2007
5		Ruwan N. S. Ratnayake, Erich F. Haratsch, Gu-Yeon Wei: A Bit-Node Centric Architecture for Low-Density Parity-Check Decoders. GLOBECOM 2007: 265-270
4		Ruwan N. S. Ratnayake, Erich F. Haratsch, Gu-Yeon Wei: Serial Sum-Product Architecture for Low-Density Parity-Check Codes. ICCCN 2007: 154-158
	2006
3		Hao Zhong, Tong Zhang, Erich F. Haratsch: High-rate quasi-cyclic LDPC codes for magnetic recording channel with low error floor. ISCAS 2006
	2004
2		Erich F. Haratsch: Trellis-based detection for high-speed data communications. Technical University Munich 2004: 1-161
	2000
1		Erich F. Haratsch, Andrew J. Blanksby, Kamran Azadet: Reduced-State Sequence Estimation with Tap-Selectable Decision-Feedback. ICC (1) 2000: 372-376

Coauthor Index

1	Kamran Azadet	[1]
2	Mudit Bhargava	[6]
3	Andrew J. Blanksby	[1]
4	Yu Cai	[6] [7] [8]
5	Ken Mai	[6] [7] [8]
6	Mark McCartney	[6] [7]
7	Onur Mutlu	[8]
8	Ruwan N. S. Ratnayake	[4] [5]
9	Gu-Yeon Wei	[4] [5]
10	Tong Zhang	[3]
11	Hao Zhong	[3]

Colors in the list of coauthors

Last update Thu May 31 18:55:10 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page