 | 2012 |
| 10 |  | Yuko Hara,
Hiroyuki Tomiyama:
Clock-constrained simultaneous allocation and binding for multiplexer optimization in high-level synthesis.
ASP-DAC 2012: 251-256 |
| 2010 |
| 9 |  | Toshinobu Matsuba,
Yuko Hara,
Hiroyuki Tomiyama,
Shinya Honda,
Hiroaki Takada:
Aggressive Register Unsharing Based on SSA Transformation for Clock Enhancement in High-Level Synthesis.
DELTA 2010: 87-92 |
| 8 |  | Yuko Hara,
Hiroyuki Tomiyama,
Shinya Honda,
Hiroaki Takada:
Partitioning of Behavioral Descriptions with Exploiting Function-Level Parallelism.
IEICE Transactions 93-A(2): 488-499 (2010) |
| 2009 |
| 7 |  | Yuko Hara,
Hiroyuki Tomiyama,
Shinya Honda,
Hiroaki Takada:
Proposal and Quantitative Analysis of the CHStone Benchmark Program Suite for Practical C-based High-level Synthesis.
JIP 17: 242-254 (2009) |
| 2008 |
| 6 |  | Yuko Hara,
Hiroyuki Tomiyama,
Shinya Honda,
Hiroaki Takada,
Katsuya Ishii:
CHStone: A benchmark program suite for practical C-based high-level synthesis.
ISCAS 2008: 1192-1195 |
| 2007 |
| 5 |  | Yuko Hara,
Hiroyuki Tomiyama,
Shinya Honda,
Hiroaki Takada,
Katsuya Ishii:
Complexity-constrainted partitioning of sequential programs for efficient behavioral synthesis.
ACM Great Lakes Symposium on VLSI 2007: 365-370 |
| 4 |  | Yuko Hara,
Hiroyuki Tomiyama,
Shinya Honda,
Hiroaki Takada,
Katsuya Ishii:
Behavioral Synthesis of Double-Precision Floating-Point Adders with Function-Level Transformations: A Case Study.
ICESS 2007: 261-270 |
| 3 |  | Yuko Hara,
Hiroyuki Tomiyama,
Shinya Honda,
Hiroaki Takada,
Katsuya Ishii:
Function-Level Partitioning of Sequential Programs for Efficient Behavioral Synthesis.
IEICE Transactions 90-A(12): 2853-2862 (2007) |
| 2 |  | Yuko Hara,
Hiroyuki Tomiyama,
Shinya Honda,
Hiroaki Takada:
Function Call Optimization for Efficient Behavioral Synthesis.
IEICE Transactions 90-A(9): 2032-2036 (2007) |
| 2006 |
| 1 |  | Yuko Hara,
Hiroyuki Tomiyama,
Shinya Honda,
Hiroaki Takada:
Function Call Optimization in Behavioral Synthesis.
DSD 2006: 522-529 |