 | 2011 |
|---|
| 5 |       | Mohammad Shihabul Haque,
Jorgen Peddersen,
Sri Parameswaran:
CIPARSim: Cache intersection property assisted rapid single-pass FIFO cache simulation technique.
ICCAD 2011: 126-133 |
| 2010 |
|---|
| 4 | | Mohammad Shihabul Haque,
Jorgen Peddersen,
Andhi Janapsatya,
Sri Parameswaran:
SCUD: a fast single-pass L1 cache simulation approach for embedded processors with round-robin replacement policy.
DAC 2010: 356-361 |
| 3 | | Haris Javaid,
Andhi Janapsatya,
Mohammad Shihabul Haque,
Sri Parameswaran:
Rapid runtime estimation methods for pipelined MPSoCs.
DATE 2010: 363-368 |
| 2 | | Mohammad Shihabul Haque,
Jorgen Peddersen,
Andhi Janapsatya,
Sri Parameswaran:
DEW: A fast level 1 cache simulation approach for embedded processors with FIFO replacement policy.
DATE 2010: 496-501 |
| 2009 |
|---|
| 1 | | Mohammad Shihabul Haque,
Andhi Janapsatya,
Sri Parameswaran:
SuSeSim: a fast simulation strategy to find optimal L1 cache configuration for embedded systems.
CODES+ISSS 2009: 295-304 |
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