Takahiro Hanyu

	2012
71		Shoun Matsunaga, Masanori Natsui, Shoji Ikeda, Katsuya Miura, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu: Implementation of a perpendicular MTJ-based read-disturb-tolerant 2T-2R nonvolatile TCAM based on a reversed current reading scheme. ASP-DAC 2012: 475-476
	2011
70		Takahiro Hanyu: Instant power-on nonvolatile FPGA based on MTJ/MOS-hybrid circuitry. ACM Great Lakes Symposium on VLSI 2011: 437-438
69		Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu: Interconnect-fault-resilient delay-insensitive asynchronous communication link based on current-flow monitoring. DATE 2011: 776-781
68		Takao Kawano, Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu: Adjacent-State monitoring based fine-grained power-gating scheme for a low-power asynchronous pipelined system. ISCAS 2011: 2067-2070
67		Naoya Onizawa, Vincent C. Gaudet, Takahiro Hanyu: Low-Energy Asynchronous Interleaver for Clockless Fully Parallel LDPC Decoding. IEEE Trans. on Circuits and Systems 58-I(8): 1933-1943 (2011)
66		Satoru Hanzawa, Takahiro Hanyu: Design of an 8-nsec 72-bit-Parallel-Search Content-Addressable Memory Using a Phase-Change Device. IEICE Transactions 94-C(8): 1302-1310 (2011)
	2010
65		Naoya Onizawa, Takahiro Hanyu: High-throughput protocol converter based on an independent encoding/decoding scheme for asynchronous Network-on-Chip. ISCAS 2010: 157-160
64		Atsushi Matsumoto, Naoya Onizawa, Takahiro Hanyu: One-Color Two-Phase Asynchronous Communication Links Based on Multiple-Valued Simultaneous Control. ISMVL 2010: 211-216
63		Masanori Natsui, Takashi Arimitsu, Takahiro Hanyu: Low-Energy Pipelined Multiple-Valued Current-Mode Circuit with 8-Level Static Current-Source Control. ISMVL 2010: 235-240
62		Naoya Onizawa, Tomoyoshi Funazaki, Atsushi Matsumoto, Takahiro Hanyu: Accurate Asynchronous Network-on-Chip Simulation Based on a Delay-Aware Model. ISVLSI 2010: 357-362
61		Takahiro Hanyu: Special session 8B: New topic MOS/MTJ-hybrid circuit with nonvolatile logic-in-memory architecture and its impact. VTS 2010: 258
60		Naoya Onizawa, Takahiro Hanyu, Vincent C. Gaudet: Design of High-Throughput Fully Parallel LDPC Decoders Based on Wire Partitioning. IEEE Trans. VLSI Syst. 18(3): 482-489 (2010)
59		Masashi Kamiyanagi, Fumitaka Iga, Shoji Ikeda, Katsuya Miura, Jun Hayakawa, Haruhiro Hasegawa, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh: Transient Characteristic of Fabricated Magnetic Tunnel Junction (MTJ) Programmed with CMOS Circuit. IEICE Transactions 93-C(5): 602-607 (2010)
58		Fumitaka Iga, Masashi Kamiyanagi, Shoji Ikeda, Katsuya Miura, Jun Hayakawa, Haruhiro Hasegawa, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh: Study of the DC Performance of Fabricated Magnetic Tunnel Junction Integrated on Back-End Metal Line of CMOS Circuits. IEICE Transactions 93-C(5): 608-613 (2010)
57		Hirokatsu Shirahama, Takashi Matsuura, Masanori Natsui, Takahiro Hanyu: Energy-Aware Multiple-Valued Current-Mode Sequential Circuits Using a Completion-Detection Scheme. IEICE Transactions 93-D(8): 2080-2088 (2010)
56		Naoya Onizawa, Takahiro Hanyu: Highly Reliable Multiple-Valued One-Phase Signalling for an Asynchronous On-Chip Communication Link. IEICE Transactions 93-D(8): 2089-2099 (2010)
	2009
55		Shoun Matsunaga, Jun Hayakawa, Shoji Ikeda, Katsuya Miura, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu: MTJ-based nonvolatile logic-in-memory circuit, future prospects and issues. DATE 2009: 433-435
54		Yo Ohtake, Naoya Onizawa, Takahiro Hanyu: High-performance Asynchronous Intra-chip Communication Link based on a Multiple-valued Current-mode Single-track Scheme. ISCAS 2009: 1000-1003
53		Naoya Onizawa, Takahiro Hanyu: Robust Multiple-Valued Current-Mode Circuit Components Based on Adaptive Reference-Voltage Control. ISMVL 2009: 36-41
52		Takashi Matsuura, Hirokatsu Shirahama, Masanori Natsui, Takahiro Hanyu: Timing-Variation-Aware Multiple-Valued Current-Mode Circuit for a Low-Power Pipelined System. ISMVL 2009: 60-65
51		Naoya Onizawa, Takahiro Hanyu, Vincent C. Gaudet: High-Throughput Bit-Serial LDPC Decoder LSI Based on Multiple-Valued Asynchronous Interleaving. IEICE Transactions 92-C(6): 867-874 (2009)
	2008
50		Akihiro Hirosaki, Masatomo Miura, Atsushi Matsumoto, Takahiro Hanyu: Vth-Variation Compensation of Multiple-Valued Current-Mode Circuit Using TMR Devices. ISMVL 2008: 14-19
49		Tasuku Nagai, Naoya Onizawa, Takahiro Hanyu: High-Speed Timing Verification Scheme Using Delay Tables for a Large-Scaled Multiple-Valued Current-Mode Circuit. ISMVL 2008: 70-75
48		Hirokatsu Shirahama, Takahiro Hanyu: Design of High-Performance Quaternary Adders Based on Output-Generator Sharing. ISMVL 2008: 8-13
47		Kazuyasu Mizusawa, Naoya Onizawa, Takahiro Hanyu: Power-Aware Asynchronous Peer-to-Peer Duplex Communication System Based on Multiple-Valued One-Phase Signaling. IEICE Transactions 91-C(4): 581-588 (2008)
46		Masatomo Miura, Takahiro Hanyu: Highly Reliable Multiple-Valued Current-Mode Comparator Based on Active-Load Dual-Rail Operation. IEICE Transactions 91-C(4): 589-594 (2008)
	2007
45		Shoun Matsunaga, Takahiro Hanyu, Hiromitsu Kimura, T. Nakamura, H. Takasu: Implementation of a Standby-Power-Free CAM Based on Complementary Ferroelectric-Capacitor Logic. ASP-DAC 2007: 116-117
44		Hirokatsu Shirahama, Akira Mochizuki, Takahiro Hanyu, Masami Nakajima, Kazutami Arimoto: Design of a Processing Element Based on Quaternary Differential Logic for a Multi-Core SIMD Processor. ISMVL 2007: 43
43		Tomohiro Takahashi, Kazuyasu Mizusawa, Takahiro Hanyu: Asynchronous Peer-to-Peer Simplex/Duplex-Compatible Communication System Using a One-Phase Signaling Scheme. ISMVL 2007: 44
42		Akira Mochizuki, Masatomo Miura, Takahiro Hanyu: High-Performance Multiple-Valued Comparator Based on Active-Load Dual-Rail Differential Logic for Crosstalk-Noise Reduction. ISMVL 2007: 57
41		Akira Mochizuki, Hirokatsu Shirahama, Takahiro Hanyu: Design and Evaluation of a 54 x 54-bit Multiplier Based on Differential-Pair Circuitry. IEICE Transactions 90-C(4): 683-691 (2007)
	2006
40		Akira Mochizuki, Takeshi Kitamura, Hirokatsu Shirahama, Takahiro Hanyu: Design of a Microprocessor Datapath Using Four-Valued Differential-Pair Circuits. ISMVL 2006: 14
39		Akira Mochizuki, Takahiro Hanyu: Highly reliable Multiple-Valued Circuit Based on Dual-Rail Differential Logic. ISMVL 2006: 5
38		Takahiro Hanyu: Special Section on Novel Device Architectures and System Integration Technologies. IEICE Transactions 89-C(11): 1491 (2006)
37		Naoya Onizawa, Takahiro Hanyu: Design and Evaluation of a NULL-Convention Circuit Based on Dual-Rail Current-Mode Differential Logic. IEICE Transactions 89-C(11): 1575-1580 (2006)
36		Akira Mochizuki, Hirokatsu Shirahama, Takahiro Hanyu: Design of a Low-Power Quaternary Flip-Flop Based on Dynamic Differential Logic. IEICE Transactions 89-C(11): 1591-1597 (2006)
35		Tomohiro Takahashi, Takahiro Hanyu: Implementation of a High-Speed Asynchronous Data-Transfer Chip Based on Multiple-Valued Current-Signal Multiplexing. IEICE Transactions 89-C(11): 1598-1604 (2006)
	2005
34		Naoya Onizawa, Akira Mochizuki, Takahiro Hanyu: Multiple-Valued Duplex Asynchronous Data Transfer Scheme for Interleaving in LDPC Decoders. ISMVL 2005: 138-143
33		Akira Mochizuki, Hiromitsu Kimura, Mitsuru Ibuki, Takahiro Hanyu: TMR-Based Logic-in-Memory Circuit for Low-Power VLSI. IEICE Transactions 88-A(6): 1408-1415 (2005)
	2004
32		Akira Mochizuki, Takashi Takeuchi, Takahiro Hanyu: Intra-Chip Address-Presetting Data-Transfer Scheme Using Four-Valued Encoding. ISMVL 2004: 192-197
31		Tomohiro Takahashi, Takahiro Hanyu: Multiple-Valued Multiple-Rail Encoding Scheme for Low-Power Asynchronous Communication. ISMVL 2004: 20-25
30		Hiromitsu Kimura, Kostas Pagiamtzis, Ali Sheikholeslami, Takahiro Hanyu: A Study of Multiple-Valued Magnetoresistive RAM (MRAM) Using Binary MTJ Devices. ISMVL 2004: 340-345
	2003
29		Takahiro Hanyu, Akira Mochizuki, Michitaka Kameyama: Multiple-Valued Dynamic Source-Coupled Logic. ISMVL 2003: 207-212
28		Takahiro Hanyu, Tomohiro Takahashi, Michitaka Kameyama: Bidirectional Data Transfer Based Asynchronous VLSI System Using Multiple-Valued Current Mode Logic. ISMVL 2003: 99-104
	2002
27		Hiromitsu Kimura, Takahiro Hanyu, Michitaka Kameyama: Multiple-Valued Logic-in-Memory VLSI Based on Ferroelectric Capacitor Storage and Charge Addition. ISMVL 2002: 161-
26		Tsukasa Ike, Takahiro Hanyu, Michitaka Kameyama: Fully Source-Coupled Logic Based Multiple-Valued VLSI. ISMVL 2002: 270-275
	2001
25		Takahiro Hanyu, Michitaka Kameyama, Katsuhiko Shimabukuro, C. Zukeran: Multiple-Valued Mask-Programmable Logic Array Using One-Transistor Universal-Literal Circuits. ISMVL 2001: 167-172
24		Tsukasa Ike, Takahiro Hanyu, Michitaka Kameyama: Dual-Rail Multiple-Valued Current-Mode VLSI with Biasing Current Sources. ISMVL 2001: 21-26
23		Takahiro Hanyu: Challenge of a Multiple-Valued Technology in Recent Deep-Submicron VLSI. ISMVL 2001: 241-
	2000
22		Takahiro Hanyu, Tsukasa Ike, Michitaka Kameyama: Low-Power Dual-Rail Multiple-Valued Current-Mode Logic Circuit Using Multiple Input-Signal Levels. ISMVL 2000: 382-
21		Takahiro Hanyu, Hiromitsu Kimura, Michitaka Kameyama: DRAM-Cell-Based Multiple-Valued Logic-in-Memory VLSI with Charge Addition and Charge Storage. ISMVL 2000: 423-429
20		Shunichi Kaeriyama, Takahiro Hanyu, Michitaka Kameyama: Arithmetic-Oriented Multiple-Valued Logic-in-Memory VLSI Based on Current-Mode Logic. ISMVL 2000: 438-
19		Takahiro Hanyu, Tsukasa Ike, Michitaka Kameyama: Integration of asynchronous and self-checking multiple-valued current-mode circuits based on dual-rail differential logic. PRDC 2000: 27-36
	1999
18		Takahiro Hanyu, Tsukasa Ike, Michitaka Kameyama: Self-Checking Multiple-Valued Circuit Based on Dual-Rail Current-Mode Differential Logic. ISMVL 1999: 275-279
17		Takahiro Hanyu, Hiromitsu Kimura, Michitaka Kameyama: Multiple-Valued Content-Addressable Memory Using Metal-Ferroelectric-Semiconductor FETs. ISMVL 1999: 30-35
	1998
16		Takahiro Hanyu, Takahiro Saito, Michitaka Kameyama: Asynchronous Multiple-Valued VLSI System Based on Dual-Rail Current-Mode Differential Logic. ISMVL 1998: 134-139
15		Takahiro Hanyu, Kaname Teranishi, Michitaka Kameyama: Multiple-Valued Floating-Gate-MOS Pass Logic and its Application to Logic-in-Memory VLSI. ISMVL 1998: 270-275
14		Takahiro Saito, Takahiro Hanyu, Michitaka Kameyama: Optimal design of a current-mode deep-submicron multiple-valued integrated circuit and application. Systems and Computers in Japan 29(11): 40-47 (1998)
13		Takahiro Hanyu, Kaname Teranishi, Michitaka Kameyama: Design and evaluation of a digit-parallel multiple-valued content-addressable memory. Systems and Computers in Japan 29(11): 48-54 (1998)
	1997
12		Takahiro Hanyu, Manabu Arakaki, Michitaka Kameyama: One-Transistor-Cell 4-Valued Universal-Literal CAM for Cellular Logic Image Processing. ISMVL 1997: 175-
	1996
11		Takahiro Hanyu, Manabu Arakaki, Michitaka Kameyama: Quaternary Universal-Literal CAM for Cellular Logic Image Processing. ISMVL 1996: 224-229
10		Ali Sheikholeslami, P. Glenn Gulak, Takahiro Hanyu: A Multiple-Valued Ferroelectric Content-Addressable Memory. ISMVL 1996: 74-79
	1995
9		Takahiro Hanyu, Akira Mochizuki, Michitaka Kameyama: Multiple-Valued Arithmetic Integrated Circuits Based on 1.5V-Supply Dual-Rail Source-Coupled Logic. ISMVL 1995: 64-
8		Xiaowei Deng, Takahiro Hanyu, Michitaka Kameyama: Quantum Device Model-Based Super Pass Gate for Multiple-Valued Digital Systems. ISMVL 1995: 92-97
7		Xiaowei Deng, Takahiro Hanyu, Michitaka Kameyama: Quantum-Device-Oriented Multiple-Valued Logic System Based on a Super Pass Gate. IEICE Transactions 78-D(8): 951-958 (1995)
	1994
6		Takahiro Hanyu, Akira Mochizuki, Michitaka Kameyama: Multiple-Valued Current-Mode MOS Integrated Circuits Based on Dual-Rail Source-Coupled Logic. ISMVL 1994: 19-26
	1993
5		Satoshi Aragaki, Takahiro Hanyu, Tatsuo Higuchi: A Multiple-Valued Content-Addressable Memory Using Logic-Value Conversion and Threshold Functions. ISMVL 1993: 170-175
	1992
4		Takahiro Hanyu, Kouichi Takeda, Tatsuo Higuchi: Design of a Multiple-Valued Rule-Programmable Matching VLSI Chip for Real-Time Rule-Based Systems. ISMVL 1992: 274-281
	1991
3		Takahiro Hanyu, Yasushi Kojima, Tatsuo Higuchi: A Multiple-Valued Logic Artay VLSI Based on Two-Transistor Delta Literal Circuit and Its Application to Real-Time Reasoning Systems. ISMVL 1991: 16-23
2		Takahiro Hanyu, Tatsuo Higuchi: A Floating-Gate-MOS-Based Multiple-Valued Associative Memory. ISMVL 1991: 24-31
	1990
1		Takahiro Hanyu, Tatsuo Higuchi: Design of a High-Density Multiple-Valued Content-Addressable Memory Based on Floating-Gate MOS Devices. ISMVL 1990: 18-23

Coauthor Index

1	Satoshi Aragaki	[5]
2	Manabu Arakaki	[11] [12]
3	Takashi Arimitsu	[63]
4	Kazutami Arimoto	[44]
5	Xiaowei Deng	[7] [8]
6	Tetsuo Endoh	[55] [58] [59] [71]
7	Tomoyoshi Funazaki	[62]
8	Vincent C. Gaudet	[51] [60] [67]
9	P. Glenn Gulak	[10]
10	Satoru Hanzawa	[66]
11	Haruhiro Hasegawa	[58] [59]
12	Jun Hayakawa	[55] [58] [59]
13	Tatsuo Higuchi	[1] [2] [3] [4] [5]
14	Akihiro Hirosaki	[50]
15	Mitsuru Ibuki	[33]
16	Fumitaka Iga	[58] [59]
17	Tsukasa Ike	[18] [19] [22] [24] [26]
18	Shoji Ikeda	[55] [58] [59] [71]
19	Shunichi Kaeriyama	[20]
20	Michitaka Kameyama	[6] [7] [8] [9] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [24] [25] [26] [27] [28] [29]
21	Masashi Kamiyanagi	[58] [59]
22	Takao Kawano	[68]
23	Hiromitsu Kimura	[17] [21] [27] [30] [33] [45]
24	Takeshi Kitamura	[40]
25	Yasushi Kojima	[3]
26	Atsushi Matsumoto	[50] [62] [64] [68] [69]
27	Shoun Matsunaga	[45] [55] [71]
28	Takashi Matsuura	[52] [57]
29	Katsuya Miura	[55] [58] [59] [71]
30	Masatomo Miura	[42] [46] [50]
31	Kazuyasu Mizusawa	[43] [47]
32	Akira Mochizuki	[6] [9] [29] [32] [33] [34] [36] [39] [40] [41] [42] [44]
33	Tasuku Nagai	[49]
34	Masami Nakajima	[44]
35	T. Nakamura	[45]
36	Masanori Natsui	[52] [57] [63] [71]
37	Hideo Ohno	[55] [58] [59] [71]
38	Yo Ohtake	[54]
39	Naoya Onizawa	[34] [37] [47] [49] [51] [53] [54] [56] [60] [62] [64] [65] [67] [68] [69]
40	Kostas Pagiamtzis	[30]
41	Takahiro Saito	[14] [16]
42	Ali Sheikholeslami	[10] [30]
43	Katsuhiko Shimabukuro	[25]
44	Hirokatsu Shirahama	[36] [40] [41] [44] [48] [52] [57]
45	Tomohiro Takahashi	[28] [31] [35] [43]
46	H. Takasu	[45]
47	Kouichi Takeda	[4]
48	Takashi Takeuchi	[32]
49	Kaname Teranishi	[13] [15]
50	C. Zukeran	[25]

Colors in the list of coauthors

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