Frank Hannig

	2012
56		Richard Membarth, Jan-Hugo Lupp, Frank Hannig, Jürgen Teich, Mario Körner, Wieland Eckert: Dynamic Task-Scheduling and Resource Management for GPU Accelerators in Medical Imaging. ARCS 2012: 147-159
55		Sascha Roloff, Frank Hannig, Jürgen Teich: Approximate time functional simulation of resource-aware programming concepts for heterogeneous MPSoCs. ASP-DAC 2012: 187-192
	2011
54		Joseph R. Cavallaro, Milos D. Ercegovac, Frank Hannig, Paolo Ienne, Earl E. Swartzlander Jr., Alexandre F. Tenca: 22nd IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2011, Santa Monica, CA, USA, Sept. 11-14, 2011 IEEE 2011
53		Richard Membarth, Frank Hannig, Jürgen Teich, Mario Körner, Wieland Eckert: Frameworks for Multi-core Architectures: A Comprehensive Evaluation Using 2D/3D Image Registration. ARCS 2011: 62-73
52		Vahid Lari, Andriy Narovlyanskyy, Frank Hannig, Jürgen Teich: Decentralized dynamic resource management support for massively parallel processor arrays. ASAP 2011: 87-94
51		Vahid Lari, Frank Hannig, Jürgen Teich: Distributed Resource Reservation in Massively Parallel Processor Arrays. IPDPS Workshops 2011: 318-321
50		Georgia Kouveli, Frank Hannig, Jan-Hugo Lupp, Jürgen Teich: Towards Resource Aware Programming on Intel's Single-Chip Cloud Computer Processor. MARC Symposium 2011: 111-114
49		Srinivas Boppu, Frank Hannig, Jürgen Teich, Roberto Perez-Andrade: Towards Symbolic Run-Time Reconfiguration in Tightly-Coupled Processor Arrays. ReConFig 2011: 392-397
48		Frank Hannig, Sascha Roloff, Gregor Snelting, Jürgen Teich, Andreas Zwinkau: Resource-aware programming and simulation of MPSoC architectures through extension of X10. SCOPES 2011: 48-55
47		Dmitrij Kissler, D. Gran, Zoran Salcic, Frank Hannig, Jürgen Teich: Scalable Many-Domain Power Gating in Coarse-Grained Reconfigurable Processor Arrays. Embedded Systems Letters 3(2): 58-61 (2011)
46		Dmitrij Kissler, Frank Hannig, Jürgen Teich: Efficient Evaluation of Power/Area/Latency Design Trade-Offs for Coarse-Grained Reconfigurable Processor Arrays. J. Low Power Electronics 7(1): 29-40 (2011)
	2010
45		François Charot, Frank Hannig, Jürgen Teich, Christophe Wolinski: 21st IEEE International Conference on Application-specific Systems Architectures and Processors, ASAP 2010, Rennes, France, 7-9 July 2010 IEEE 2010
44		Hritam Dutta, Frank Hannig, Moritz Schmid, Joachim Keinert: Modeling and synthesis of communication subsystems for loop accelerator pipelines. ASAP 2010: 125-132
43		Tom Vander Aa, Praveen Raghavan, Scott A. Mahlke, Bjorn De Sutter, Aviral Shrivastava, Frank Hannig: Compilation techniques for CGRAs: exploring all parallelization approaches. CODES+ISSS 2010: 185-186
42		Frank Hannig, Moritz Schmid, Jürgen Teich, Heinz Hornegger: A deeply pipelined and parallel architecture for denoising medical images. FPT 2010: 485-490
	2009
41		Frank Hannig, Hritam Dutta, Jürgen Teich: Parallelization Approaches for Hardware Accelerators - Loop Unrolling Versus Loop Partitioning. ARCS 2009: 16-27
40		Hritam Dutta, Frank Hannig, Jürgen Teich: Performance Matching of Hardware Acceleration Engines for Heterogeneous MPSoC Using Modular Performance Analysis. ARCS 2009: 233-245
39		Hritam Dutta, Jiali Zhai, Frank Hannig, Jürgen Teich: Impact of Loop Tiling on the Controller Logic of Acceleration Engines. ASAP 2009: 161-168
38		Richard Membarth, Philipp Kutzer, Hritam Dutta, Frank Hannig, Jürgen Teich: Acceleration of Multiresolution Imaging Algorithms: A Comparative Study. ASAP 2009: 211-214
37		Joachim Keinert, Hritam Dutta, Frank Hannig, Christian Haubelt, Jürgen Teich: Model-based synthesis and optimization of static multi-rate image processing algorithms. DATE 2009: 135-140
36		Vahid Lari, Frank Hannig, Jürgen Teich: System Integration of Tightly-Coupled Reconfigurable Processor Arrays and Evaluation of Buffer Size Effects on Their Performance. ICPP Workshops 2009: 528-534
35		Richard Membarth, Frank Hannig, Hritam Dutta, Jürgen Teich: Efficient Mapping of Multiresolution Image Filtering Algorithms on Graphics Processors. SAMOS 2009: 277-288
34		Dmitrij Kissler, Andreas Strawetz, Frank Hannig, Jürgen Teich: Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures. J. Low Power Electronics 5(1): 96-105 (2009)
33		Hritam Dutta, Dmitrij Kissler, Frank Hannig, Alexey Kupriyanov, Jürgen Teich, Bernard Pottier: A holistic approach for tightly coupled reconfigurable parallel processors. Microprocessors and Microsystems - Embedded Hardware Design 33(1): 53-62 (2009)
32		Frank Hannig: Scheduling Techniques for High-Throughput Loop Accelerators. University of Erlangen-Nuremberg 2009: 1-305
	2008
31		Frank Hannig, Holger Ruckdeschel, Hritam Dutta, Jürgen Teich: PARO: Synthesis of Hardware Accelerators for Multi-Dimensional Dataflow-Intensive Applications. ARC 2008: 284-289
30		Christophe Wolinski, Krzysztof Kuchcinski, Jürgen Teich, Frank Hannig: Communication Network Reconfiguration Overhead Optimization in Programmable Processor Array Architectures. DSD 2008: 345-352
29		Rainer Schaffer, Renate Merker, Frank Hannig, Jürgen Teich: Utilization of all Levels of Parallelism in a Processor Array with Subword Parallelism. DSD 2008: 391-398
28		Christophe Wolinski, Krzysztof Kuchcinski, Jürgen Teich, Frank Hannig: Optimization of Routing and Reconfiguration Overhead in Programmable Processor Array Architectures. FCCM 2008: 306-309
27		Sven Eisenhardt, Thomas Schweizer, Julio A. de Oliveira Filho, Tobias Oppold, Wolfgang Rosenstiel, Alexander Thomas, Jürgen Becker, Frank Hannig, Dmitrij Kissler, Hritam Dutta, Jürgen Teich, Heiko Hinkelmann, Peter Zipf, Manfred Glesner: Coarse-grained reconfiguration. FPL 2008: 349
26		Christophe Wolinski, Krzysztof Kuchcinski, Jürgen Teich, Frank Hannig: Area and reconfiguration time minimization of the communication network in regular 2D reconfigurable architectures. FPL 2008: 391-396
25		Dmitrij Kissler, Andreas Strawetz, Frank Hannig, Jürgen Teich: Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures. PATMOS 2008: 307-317
	2007
24		Alexey Kupriyanov, Frank Hannig, Dmitrij Kissler, Jürgen Teich, Julien Lallet, Olivier Sentieys, Sébastien Pillement: Modeling of Interconnection Networks in Massively Parallel Processor Architectures. ARCS 2007: 268-282
23		Jürgen Teich, Frank Hannig, Holger Ruckdeschel, Hritam Dutta, Dmitrij Kissler, Andrej Stravet: A Unified Retargetable Design Methodology for Dedicated and Re-Programmable Multiprocessor Arrays: Case Study and Quantitative Evaluation. ERSA 2007: 14-24
22		Hritam Dutta, Frank Hannig, Alexey Kupriyanov, Dmitrij Kissler, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Bernard Pottier: Massively Parallel Processor Architectures: A Co-design Approach. ReCoSoC 2007: 61-68
21		Alexey Kupriyanov, Dmitrij Kissler, Frank Hannig, Jürgen Teich: Efficient event-driven simulation of parallel processor architectures. SCOPES 2007: 71-80
20		Hritam Dutta, Frank Hannig, Holger Ruckdeschel, Jürgen Teich: Efficient control generation for mapping nested loop programs onto processor arrays. Journal of Systems Architecture 53(5-6): 300-309 (2007)
	2006
19		Hritam Dutta, Frank Hannig, Jürgen Teich: Controller Synthesis for Mapping Partitioned Programs on Array Architectures. ARCS 2006: 176-190
18		Hritam Dutta, Frank Hannig, Jürgen Teich, Benno Heigl, Heinz Hornegger: A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing. ASAP 2006: 331-340
17		Dmitrij Kissler, Alexey Kupriyanov, Frank Hannig, Dirk Koch, Jürgen Teich: A Generic Framework for Rapid Prototyping of System-on-Chip Designs. CDES 2006: 189-195
16		Hritam Dutta, Frank Hannig, Jürgen Teich: Hierarchical Partitioning for Piecewise Linear Algorithms. PARELEC 2006: 153-160
15		Dmitrij Kissler, Frank Hannig, Alexey Kupriyanov, Jürgen Teich: A Dynamically Reconfigurable Weakly Programmable Processor Array Architecture Template. ReCoSoC 2006: 31-37
14		Frank Hannig, Hritam Dutta, Jürgen Teich: Mapping a class of dependence algorithms to coarse-grained reconfigurable arrays: architectural parameters and methodology. IJES 2(1/2): 114-127 (2006)
	2005
13		Thomas Schlichter, Christian Haubelt, Frank Hannig, Jürgen Teich: Using Symbolic Feasibility Tests during Design Space Exploration of Heterogeneous Multi-Processor Systems. ASAP 2005: 9-14
12		Frank Hannig, Jürgen Teich: Output Serialization for FPGA-based and Coarse-grained Processor Arrays. ERSA 2005: 78-84
11		Jan van der Veen, Sándor P. Fekete, Mateusz Majer, Ali Ahmadinia, Christophe Bobda, Frank Hannig, Jürgen Teich: Defragmenting the Module Layout of a Partially Reconfigurable Device. ERSA 2005: 92-104
10		Frank Hannig, Hritam Dutta, Alexey Kupriyanov, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Ronan Keryell, Bernard Pottier, Daniel Chillet, Daniel Menard, Olivier Sentieys: Co-Design of Massively Parallel Embedded Processor Architectures. ReCoSoC 2005: 27-34
9		Holger Ruckdeschel, Hritam Dutta, Frank Hannig, Jürgen Teich: Automatic FIR Filter Generation for FPGAs. SAMOS 2005: 51-61
8		Jan van der Veen, Sándor P. Fekete, Ali Ahmadinia, Christophe Bobda, Frank Hannig, Jürgen Teich: Defragmenting the Module Layout of a Partially Reconfigurable Device CoRR abs/cs/0505005: (2005)
	2004
7		Frank Hannig, Jürgen Teich: Resource Constrained and Speculative Scheduling of an Algorithm Class with Run-Time Dependent Conditionals. ASAP 2004: 17-27
6		Frank Hannig, Hritam Dutta, Jürgen Teich: Mapping of Regular Nested Loop Programs to Coarse-Grained Reconfigurable Arrays - Constraints and Methodology. IPDPS 2004
5		Frank Hannig, Jürgen Teich: Dynamic Piecewise Linear/Regular Algorithms. PARELEC 2004: 79-84
4		Alexey Kupriyanov, Frank Hannig, Jürgen Teich: High-Speed Event-Driven RTL Compiled Simulation. SAMOS 2004: 519-529
	2002
3		Marcus Bednara, Frank Hannig, Jürgen Teich: Generation of Distributed Loop Control. Embedded Processor Design Challenges 2002: 154-170
2		Frank Hannig, Jürgen Teich: Energy estimation of nested loop programs. SPAA 2002: 149-150
	2001
1		Frank Hannig, Jürgen Teich: Design Space Exploration for Massively Parallel Processor Arrays. PaCT 2001: 51-65

Coauthor Index

1	Tom Vander Aa	[43]
2	Ali Ahmadinia	[8] [11]
3	Jürgen Becker	[27]
4	Marcus Bednara	[3]
5	Christophe Bobda	[8] [11]
6	Srinivas Boppu	[49]
7	Joseph R. Cavallaro	[54]
8	François Charot	[45]
9	Daniel Chillet	[10]
10	Hritam Dutta	[6] [9] [10] [14] [16] [18] [19] [20] [22] [23] [27] [31] [33] [35] [37] [38] [39] [40] [41] [44]
11	Wieland Eckert	[53] [56]
12	Sven Eisenhardt	[27]
13	Milos D. Ercegovac	[54]
14	Sándor P. Fekete	[8] [11]
15	Julio A. de Oliveira Filho	[27]
16	Manfred Glesner	[27]
17	D. Gran	[47]
18	Christian Haubelt	[13] [37]
19	Benno Heigl	[18]
20	Heiko Hinkelmann	[27]
21	Heinz Hornegger	[18] [42]
22	Paolo Ienne	[54]
23	Joachim Keinert	[37] [44]
24	Ronan Keryell	[10]
25	Dmitrij Kissler	[15] [17] [21] [22] [23] [24] [25] [27] [33] [34] [46] [47]
26	Dirk Koch	[17]
27	Mario Körner	[53] [56]
28	Georgia Kouveli	[50]
29	Krzysztof Kuchcinski	[26] [28] [30]
30	Alexey Kupriyanov	[4] [10] [15] [17] [21] [22] [24] [33]
31	Philipp Kutzer	[38]
32	Julien Lallet	[24]
33	Vahid Lari	[36] [51] [52]
34	Jan-Hugo Lupp	[50] [56]
35	Scott A. Mahlke	[43]
36	Mateusz Majer	[11]
37	Richard Membarth	[35] [38] [53] [56]
38	Daniel Menard	[10]
39	Renate Merker	[10] [22] [29]
40	Andriy Narovlyanskyy	[52]
41	Tobias Oppold	[27]
42	Roberto Perez-Andrade	[49]
43	Sébastien Pillement	[24]
44	Bernard Pottier	[10] [22] [33]
45	Praveen Raghavan	[43]
46	Sascha Roloff	[48] [55]
47	Wolfgang Rosenstiel	[27]
48	Holger Ruckdeschel	[9] [20] [23] [31]
49	Zoran A. Salcic (Zoran Salcic)	[47]
50	Rainer Schaffer	[10] [22] [29]
51	Thomas Schlichter	[13]
52	Moritz Schmid	[42] [44]
53	Thomas Schweizer	[27]
54	Olivier Sentieys	[10] [24]
55	Aviral Shrivastava	[43]
56	Sebastian Siegel	[10] [22]
57	Gregor Snelting	[48]
58	Andrej Stravet	[23]
59	Andreas Strawetz	[25] [34]
60	Bjorn De Sutter	[43]
61	Earl E. Swartzlander Jr.	[54]
62	Jürgen Teich	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [25] [26] [27] [28] [29] [30] [31] [33] [34] [35] [36] [37] [38] [39] [40] [41] [42] [45] [46] [47] [48] [49] [50] [51] [52] [53] [55] [56]
63	Alexandre F. Tenca	[54]
64	Alexander Thomas	[27]
65	Jan van der Veen	[8] [11]
66	Christophe Wolinski	[26] [28] [30] [45]
67	Jiali Zhai	[39]
68	Peter Zipf	[27]
69	Andreas Zwinkau	[48]

Colors in the list of coauthors

Last update Thu May 31 18:55:10 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page