Toshihiro Hanawa

	2011
21		Shin'ichi Miura, Toshihiro Hanawa, Taisuke Boku, Mitsuhisa Sato: XMCAPI: Inter-core Communication Interface on Multi-chip Embedded Systems. EUC 2011: 397-402
20		Toshihiro Hanawa, Taisuke Boku, Shin'ichi Miura, Mitsuhisa Sato, Kazutami Arimoto: PEARL and PEACH: A Novel PCI Express Direct Link and Its Implementation. IPDPS Workshops 2011: 871-879
19		Sugako Otani, Hiroyuki Kondo, Itaru Nonomura, Atsuyuki Ikeya, Minoru Uemura, Yasushi Hayakawa, Takeshi Oshita, Satoshi Kaneko, Katsushi Asahina, Kazutami Arimoto, Shin'ichi Miura, Toshihiro Hanawa, Taisuke Boku, Mitsuhisa Sato: An 80Gb/s dependable communication SoC with PCI express I/F and 8 CPUs. ISSCC 2011: 266-268
18		Sugako Otani, Hiroyuki Kondo, Itaru Nonomura, Toshihiro Hanawa, Shin'ichi Miura, Taisuke Boku: Peach: A Multicore Communication System on Chip with PCI Express. IEEE Micro 31(6): 39-50 (2011)
	2010
17		Mitsuhisa Sato, Toshihiro Hanawa, Matthias S. Müller, Barbara M. Chapman, Bronis R. de Supinski: Beyond Loop Level Parallelism in OpenMP: Accelerators, Tasking and More, 6th Internationan Workshop on OpenMP, IWOMP 2010, Tsukuba, Japan, June 14-16, 2010, Proceedings Springer 2010
16		Takayuki Banzai, Hitoshi Koizumi, Ryo Kanbayashi, Takayuki Imada, Toshihiro Hanawa, Mitsuhisa Sato: D-Cloud: Design of a Software Testing Environment for Reliable Distributed Systems Using Cloud Computing Technology. CCGRID 2010: 631-636
15		Toshihiro Hanawa, Takayuki Banzai, Hitoshi Koizumi, Ryo Kanbayashi, Takayuki Imada, Mitsuhisa Sato: Large-Scale Software Testing Environment Using Cloud Computing Technology for Dependable Parallel and Distributed Systems. ICST Workshops 2010: 428-433
14		Toshihiro Hanawa, Hitoshi Koizumi, Takayuki Banzai, Mitsuhisa Sato, Shin'ichi Miura, Tadatoshi Ishii, Hidehisa Takamizawa: Customizing Virtual Machine with Fault Injector by Integrating with SpecC Device Model for a Software Testing Environment D-Cloud. PRDC 2010: 47-54
	2009
13		Taiga Yonemoto, Shin'ichi Miura, Toshihiro Hanawa, Taisuke Boku, Mitsuhisa Sato: Flexible Multi-link Ethernet Binding System for PC Clusters with Asymmetric Topology. ICPADS 2009: 49-56
12		Shin'ichi Miura, Toshihiro Hanawa, Taiga Yonemoto, Taisuke Boku, Mitsuhisa Sato: RI2N/DRV: Multi-link ethernet for high-bandwidth and fault-tolerant network on PC clusters. IPDPS 2009: 1-7
11		Yutaka Ishikawa, Hajime Fujita, Toshiyuki Maeda, Motohiko Matsuda, Midori Sugaya, Mitsuhisa Sato, Toshihiro Hanawa, Shin'ichi Miura, Taisuke Boku, Yuki Kinebuchi, Lei Sun, Tatsuo Nakajima, Jin Nakazawa, Hideyuki Tokuda: Towards an Open Dependable Operating System. ISORC 2009: 20-27
10		Toshihiro Hanawa, Mitsuhisa Sato, Jinpil Lee, Takayuki Imada, Hideaki Kimura, Taisuke Boku: Evaluation of Multicore Processors for Embedded Systems by Parallel Benchmark Program Using OpenMP. IWOMP 2009: 15-27
	2008
9		Shin'ichi Miura, Takayuki Okamoto, Taisuke Boku, Toshihiro Hanawa, Mitsuhisa Sato: RI2N: High-bandwidth and fault-tolerant network with multi-link Ethernet for PC clusters. CLUSTER 2008: 274-279
8		Shin'ichi Miura, Taisuke Boku, Takayuki Okamoto, Toshihiro Hanawa: A dynamic routing control system for high-performance PC cluster with multi-path Ethernet connection. IPDPS 2008: 1-8
	2005
7		Toshihiro Hanawa, Toshiya Minai, Yasuki Tanabe, Hideharu Amano: Implementation of ISIS-SimpleScalar. PDPTA 2005: 117-123
6		Takashi Midorikawa, Daisuke Shiraishi, Masayoshi Shigeno, Yasuki Tanabe, Toshihiro Hanawa, Hideharu Amano: The performance of SNAIL-2 (a SSS-MIN connected multiprocessor with cache coherent mechanism). Parallel Computing 31(3-4): 352-370 (2005)
	2003
5		Yasuki Tanabe, Takashi Midorikawa, Daisuke Shiraishi, Masayoshi Shigeno, Toshihiro Hanawa, Hideharu Amano: Performance Evaluation of 3-Dimensional MIN with Cache Consistency Maintenance Mechanism. PDPTA 2003: 1148-1154
	1999
4		Junji Yamamoto, Takashi Fujiwara, T. Komeda, Takayuki Kamei, Toshihiro Hanawa, Hideharu Amano: Performance evaluation of SNAIL: A multiprocessor based on the simple serial synchronized multistage interconnection network architecture. Parallel Computing 25(9): 1081-1103 (1999)
	1998
3		Takashi Midorikawa, Takayuki Kamei, Toshihiro Hanawa, Hideharu Amano: The MINC (Multistage Interconnection Network with Cache Control Mechanism) Chip. ASP-DAC 1998: 337-338
	1997
2		Akira Funahashi, Toshihiro Hanawa, Hideharu Amano, Tomohiro Kudoh: Adaptive Routing on the Recursive Diagonal Torus. ISHPC 1997: 171-182
	1994
1		Toshihiro Hanawa, Hideharu Amano, Yoshifumi Fujikawa: Multistage Interconnection Networks with Multiple Outlets. ICPP (1) 1994: 1-8

Coauthor Index

1	Hideharu Amano	[1] [2] [3] [4] [5] [6] [7]
2	Kazutami Arimoto	[19] [20]
3	Katsushi Asahina	[19]
4	Takayuki Banzai	[14] [15] [16]
5	Taisuke Boku	[8] [9] [10] [11] [12] [13] [18] [19] [20] [21]
6	Barbara M. Chapman	[17]
7	Yoshifumi Fujikawa	[1]
8	Hajime Fujita	[11]
9	Takashi Fujiwara	[4]
10	Akira Funahashi	[2]
11	Yasushi Hayakawa	[19]
12	Atsuyuki Ikeya	[19]
13	Takayuki Imada	[10] [15] [16]
14	Tadatoshi Ishii	[14]
15	Yutaka Ishikawa	[11]
16	Takayuki Kamei	[3] [4]
17	Ryo Kanbayashi	[15] [16]
18	Satoshi Kaneko	[19]
19	Hideaki Kimura	[10]
20	Yuki Kinebuchi	[11]
21	Hitoshi Koizumi	[14] [15] [16]
22	T. Komeda	[4]
23	Hiroyuki Kondo	[18] [19]
24	Tomohiro Kudoh	[2]
25	Jinpil Lee	[10]
26	Toshiyuki Maeda	[11]
27	Motohiko Matsuda	[11]
28	Takashi Midorikawa	[3] [5] [6]
29	Toshiya Minai	[7]
30	Shin'ichi Miura	[8] [9] [11] [12] [13] [14] [18] [19] [20] [21]
31	Matthias S. Müller	[17]
32	Tatsuo Nakajima	[11]
33	Jin Nakazawa	[11]
34	Itaru Nonomura	[18] [19]
35	Takayuki Okamoto	[8] [9]
36	Takeshi Oshita	[19]
37	Sugako Otani	[18] [19]
38	Mitsuhisa Sato	[9] [10] [11] [12] [13] [14] [15] [16] [17] [19] [20] [21]
39	Masayoshi Shigeno	[5] [6]
40	Daisuke Shiraishi	[5] [6]
41	Midori Sugaya	[11]
42	Lei Sun	[11]
43	Bronis R. de Supinski	[17]
44	Hidehisa Takamizawa	[14]
45	Yasuki Tanabe	[5] [6] [7]
46	Hideyuki Tokuda	[11]
47	Minoru Uemura	[19]
48	Junji Yamamoto	[4]
49	Taiga Yonemoto	[12] [13]

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