 | 2012 |
| 53 |  | Jianliang Gao,
Jianxin Wang,
Yinhe Han,
Lei Zhang,
Xiaowei Li:
A clustering-based scheme for concurrent trace in debugging NoC-based multicore systems.
DATE 2012: 27-32 |
| 52 |  | Guihai Yan,
Yingmin Li,
Yinhe Han,
Xiaowei Li,
Minyi Guo,
Xiaoyao Liang:
AgileRegulator: A hybrid voltage regulator scheme redeeming dark silicon for power efficiency in a multicore architecture.
HPCA 2012: 287-298 |
| 2011 |
| 51 |  | Cheng Liu,
Lei Zhang,
Yinhe Han,
Xiaowei Li:
Vertical interconnects squeezing in symmetric 3D mesh Network-on-Chip.
ASP-DAC 2011: 357-362 |
| 50 |  | Cheng Liu,
Lei Zhang,
Yinhe Han,
Xiaowei Li:
A resilient on-chip router design through data path salvaging.
ASP-DAC 2011: 437-442 |
| 49 |  | Yuanqing Cheng,
Lei Zhang,
Yinhe Han,
Jun Liu,
Xiaowei Li:
Wrapper Chain Design for Testing TSVs Minimization in Circuit-Partitioned 3D SoC.
Asian Test Symposium 2011: 181-186 |
| 48 |  | Jianbo Dong,
Lei Zhang,
Yinhe Han,
Ying Wang,
Xiaowei Li:
Wear rate leveling: lifetime enhancement of PRAM with endurance variation.
DAC 2011: 972-977 |
| 47 |  | Jianliang Gao,
Yinhe Han,
Xiaowei Li:
Eliminating data invalidation in debugging multiple-clock chips.
DATE 2011: 691-696 |
| 46 |  | Ying Wang,
Lei Zhang,
Yinhe Han,
Huawei Li,
Xiaowei Li:
Flex memory: Exploiting and managing abundant off-chip optical bandwidth.
DATE 2011: 968-973 |
| 45 |  | Binzhang Fu,
Yinhe Han,
Jun Ma,
Huawei Li,
Xiaowei Li:
An abacus turn model for time/space-efficient reconfigurable routing.
ISCA 2011: 259-270 |
| 44 |  | Guihai Yan,
Yinhe Han,
Hui Liu,
Xiaoyao Liang,
Xiaowei Li:
MicroFix: Using timing interpolation and delay sensors for power reduction.
ACM Trans. Design Autom. Electr. Syst. 16(2): 16 (2011) |
| 43 |  | Guihai Yan,
Yinhe Han,
Xiaowei Li:
ReviveNet: A Self-Adaptive Architecture for Improving Lifetime Reliability via Localized Timing Adaptation.
IEEE Trans. Computers 60(9): 1219-1232 (2011) |
| 42 |  | Guihai Yan,
Yinhe Han,
Xiaowei Li:
SVFD: A Versatile Online Fault Detection Scheme via Checking of Stability Violation.
IEEE Trans. VLSI Syst. 19(9): 1627-1640 (2011) |
| 41 |  | Binzhang Fu,
Yinhe Han,
Huawei Li,
Xiaowei Li:
A New Multiple-Round Dimension-Order Routing for Networks-on-Chip.
IEICE Transactions 94-D(4): 809-821 (2011) |
| 40 |  | Song Jin,
Yinhe Han,
Huawei Li,
Xiaowei Li:
Statistical lifetime reliability optimization considering joint effect of process variation and aging.
Integration 44(3): 185-191 (2011) |
| 2010 |
| 39 |  | Song Jin,
Yinhe Han,
Huawei Li,
Xiaowei Li:
P^(2)CLRAF: An Pre- and Post-Silicon Cooperated Circuit Lifetime Reliability Analysis Framework.
Asian Test Symposium 2010: 117-120 |
| 38 |  | Lei Zhang,
Yue Yu,
Jianbo Dong,
Yinhe Han,
Shangping Ren,
Xiaowei Li:
Performance-asymmetry-aware topology virtualization for defect-tolerant NoC-based many-core processors.
DATE 2010: 1566-1571 |
| 37 |  | Binzhang Fu,
Yinhe Han,
Huawei Li,
Xiaowei Li:
Accelerating Lightpath setup via broadcasting in binary-tree waveguide in Optical NoCs.
DATE 2010: 933-936 |
| 36 |  | Guihai Yan,
Xiaoyao Liang,
Yinhe Han,
Xiaowei Li:
Leveraging the core-level complementary effects of PVT variations to reduce timing emergencies in multi-core processors.
ISCA 2010: 485-496 |
| 35 |  | Huawei Li,
Dawen Xu,
Yinhe Han,
Kwang-Ting Cheng,
Xiaowei Li:
nGFSIM : A GPU-based fault simulator for 1-to-n detection and its applications.
ITC 2010: 343-352 |
| 34 |  | Ying Wang,
Lei Zhang,
Yinhe Han,
Huawei Li,
Xiaowei Li:
Address Remapping for Static NUCA in NoC-Based Degradable Chip-Multiprocessors.
PRDC 2010: 70-76 |
| 33 |  | Jianliang Gao,
Yinhe Han,
Xiaowei Li:
A Novel Post-Silicon Debug Mechanism Based on Suspect Window.
IEICE Transactions 93-D(5): 1175-1185 (2010) |
| 32 |  | Jun Liu,
Yinhe Han,
Xiaowei Li:
Extended Selective Encoding of Scan Slices for Reducing Test Data and Test Power.
IEICE Transactions 93-D(8): 2223-2232 (2010) |
| 31 |  | Jianbo Dong,
Lei Zhang,
Yinhe Han,
Guihai Yan,
Xiaowei Li:
Performance-asymmetry-aware scheduling for Chip Multiprocessors with static core coupling.
Journal of Systems Architecture - Embedded Systems Design 56(10): 534-542 (2010) |
| 2009 |
| 30 |  | Zichu Qi,
Hui Liu,
Xiangku Li,
Da Wang,
Yinhe Han,
Huawei Li,
Weiwu Hu:
A Scalable Scan Architecture for Godson-3 Multicore Microprocessor.
Asian Test Symposium 2009: 219-224 |
| 29 |  | Jun Liu,
Yinhe Han,
Xiaowei Li:
Extended Selective Encoding of Scan Slices for Reducing Test Data and Test Power.
Asian Test Symposium 2009: 319-324 |
| 28 |  | Song Jin,
Yinhe Han,
Lei Zhang,
Huawei Li,
Xiaowei Li,
Guihai Yan:
M-IVC: Using Multiple Input Vectors to Minimize Aging-Induced Delay.
Asian Test Symposium 2009: 437-442 |
| 27 |  | Guihai Yan,
Yinhe Han,
Xiaowei Li:
A unified online Fault Detection scheme via checking of Stability Violation.
DATE 2009: 496-501 |
| 26 |  | Guihai Yan,
Yinhe Han,
Hui Liu,
Xiaoyao Liang,
Xiaowei Li:
MicroFix: exploiting path-grained timing adaptability for improving power-performance efficiency.
ISLPED 2009: 395-400 |
| 25 |  | Jianbo Dong,
Lei Zhang,
Yinhe Han,
Guihai Yan,
Xiaowei Li:
Variation-Aware Scheduling for Chip Multiprocessors with Thread Level Redundancy.
PRDC 2009: 17-22 |
| 24 |  | Binzhang Fu,
Yinhe Han,
Huawei Li,
Xiaowei Li:
A New Multiple-Round DOR Routing for 2D Network-on-Chip Meshes.
PRDC 2009: 276-281 |
| 23 |  | Jianliang Gao,
Yinhe Han,
Xiaowei Li:
A New Post-Silicon Debug Approach Based on Suspect Window.
VTS 2009: 85-90 |
| 22 |  | Lei Zhang,
Yinhe Han,
Qiang Xu,
Xiaowei Li,
Huawei Li:
On Topology Reconfiguration for Defect-Tolerant NoC-Based Homogeneous Manycore Systems.
IEEE Trans. VLSI Syst. 17(9): 1173-1186 (2009) |
| 2008 |
| 21 |  | Lei Zhang,
Yinhe Han,
Qiang Xu,
Xiaowei Li:
Defect Tolerance in Homogeneous Manycore Processors Using Core-Level Redundancy with Unified Topology.
DATE 2008: 891-896 |
| 20 |  | Guihai Yan,
Yinhe Han,
Xiaowei Li,
Hui Liu:
BAT: Performance-Driven Crosstalk Mitigation Based on Bus-Grouping Asynchronous Transmission.
IEICE Transactions 91-C(10): 1690-1697 (2008) |
| 2007 |
| 19 |  | Yinhe Han,
Yu Hu,
Xiaowei Li,
Huawei Li,
Anshuman Chandra:
Embedded Test Decompressor to Reduce the Required Channels and Vector Memory of Tester for Complex Processor Circuit.
IEEE Trans. VLSI Syst. 15(5): 531-540 (2007) |
| 18 |  | Wei Wang,
Yu Hu,
Yinhe Han,
Xiaowei Li,
You-Sheng Zhang:
Leakage Current Optimization Techniques During Test Based on Don't Care Bits Assignment.
J. Comput. Sci. Technol. 22(5): 673-680 (2007) |
| 2006 |
| 17 |  | Tong Liu,
Huawei Li,
Xiaowei Li,
Yinhe Han:
Fast Packet Classification using Group Bit Vector.
GLOBECOM 2006 |
| 16 |  | Jie Don,
Yu Hu,
Yinhe Han,
Xiaowei Li:
An on-chip combinational decompressor for reducing test data volume.
ISCAS 2006 |
| 15 |  | Yinhe Han,
Xiaowei Li,
Huawei Li,
Anshuman Chandra:
Embedded test resource for SoC to reduce required tester channels based on advanced convolutional codes.
IEEE T. Instrumentation and Measurement 55(2): 389-399 (2006) |
| 14 |  | Yu Hu,
Yinhe Han,
Xiaowei Li,
Huawei Li,
Xiaoqing Wen:
Compression/Scan Co-design for Reducing Test Data Volume, Scan-in Power Dissipation, and Test Application Time.
IEICE Transactions 89-D(10): 2616-2625 (2006) |
| 13 |  | Yinhe Han,
Huawei Li,
Xiaowei Li,
Anshuman Chandra:
Response compaction for system-on-a-chip based on advanced convolutional codes.
Science in China Series F: Information Sciences 49(2): 262-272 (2006) |
| 2005 |
| 12 |  | Yinhe Han,
Yu Hu,
Huawei Li,
Xiaowei Li:
Theoretic analysis and enhanced X-tolerance of test response compact based on convolutional code.
ASP-DAC 2005: 53-58 |
| 11 |  | Yinhe Han,
Xiaowei Li,
Shivakumar Swaminathan,
Yu Hu,
Anshuman Chandra:
Scan Data Volume Reduction Using Periodically Alterable MUXs Decompressor.
Asian Test Symposium 2005: 372-377 |
| 10 |  | Yanzhuo Tan,
Yinhe Han,
Xiaowei Li,
Feiyin Lu,
Yuchuan Chen:
Validation analysis and test flow optimization of VLSI chip.
ISCAS (6) 2005: 5666-5669 |
| 9 |  | Ji Li,
Yinhe Han,
Xiaowei Li:
Deterministic and low power BIST based on scan slice overlapping.
ISCAS (6) 2005: 5670-5673 |
| 8 |  | Yinhe Han,
Yu Hu,
Huawei Li,
Xiaowei Li:
Using MUXs Network to Hide Bunches of Scan Chains.
ISQED 2005: 238-243 |
| 7 |  | Yinhe Han,
Yu Hu,
Xiaowei Li,
Huawei Li,
Anshuman Chandra,
Xiaoqing Wen:
Wrapper Scan Chains Design for Rapid and Low Power Testing of Embedded Cores.
IEICE Transactions 88-D(9): 2126-2134 (2005) |
| 6 |  | Yinhe Han,
Xiaowei Li,
Huawei Li,
Anshuman Chandra:
Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Tester Channels Reduction.
J. Comput. Sci. Technol. 20(2): 201-209 (2005) |
| 2004 |
| 5 |  | Yu Hu,
Yinhe Han,
Huawei Li,
Tao Lv,
Xiaowei Li:
Pair Balance-Based Test Scheduling for SOCs.
Asian Test Symposium 2004: 236-241 |
| 4 |  | Yinhe Han,
Yu Hu,
Huawei Li,
Xiaowei Li,
Anshuman Chandra:
Rapid and Energy-Efficient Testing for Embedded Cores.
Asian Test Symposium 2004: 8-13 |
| 3 |  | Yinhe Han,
Yu Hu,
Huawei Li,
Xiaowei Li,
Anshuman Chandra:
Response Compaction for Test Time and Test Pins Reduction Based on Advanced Convolutional Codes.
DFT 2004: 298-305 |
| 2 |  | Yinhe Han,
Xiaowei Li:
Simultaneous Reduction of Test Data Volume and Testing Power for Scan-Based Test.
ESA/VLSI 2004: 374-381 |
| 2003 |
| 1 |  | Yinhe Han,
Yongjun Xu,
Huawei Li,
Xiaowei Li,
Anshuman Chandra:
Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Teste.
Asian Test Symposium 2003: 440-445 |