Said Hamdioui

	2012
70		Nor Zaidi Haron, Said Hamdioui: DfT schemes for resistive open defects in RRAMs. DATE 2012: 799-804
69		Mottaqiallah Taouil, Said Hamdioui, Kees Beenakker, Erik Jan Marinissen: Test Impact on the Overall Die-to-Wafer 3D Stacked IC Cost. J. Electronic Testing 28(1): 15-25 (2012)
	2011
68		Said Hamdioui, Venkataraman Krishnaswami, Ijeoma Sandra Irobi, Zaid Al-Ars: A New Test Paradigm for Semiconductor Memories in the Nano-Era. Asian Test Symposium 2011: 347-352
67		Nor Zaidi Haron, Said Hamdioui, Nor Zaidi Haron: On Defect Oriented Testing for Hybrid CMOS/Memristor Memory. Asian Test Symposium 2011: 353-358
66		Sandra Irobi, Zaid Al-Ars, Said Hamdioui, Claude Thibeault: Testing for Parasitic Memory Effect in SRAMs. Asian Test Symposium 2011: 407-412
65		Said Hamdioui, Mottaqiallah Taouil: Yield Improvement and Test Cost Optimization for 3D Stacked ICs. Asian Test Symposium 2011: 480-485
64		Nor Zaidi Haron, Said Hamdioui: Cost-efficient fault-tolerant decoder for hybrid nanoelectronic memories. DATE 2011: 265-268
63		Sandra Irobi, Zaid Al-Ars, Said Hamdioui, Michel Renovell: Influence of parasitic memory effect on single-cell faults in SRAMs. DDECS 2011: 159-162
62		Mottaqiallah Taouil, Said Hamdioui: Stacking order impact on overall 3D die-to-wafer Stacked-IC cost. DDECS 2011: 335-340
61		Ahmed Awad, Abdallatif S. Abu-Issa, Said Hamdioui: Reducing Test Power for Embedded Memories. DFT 2011: 112-119
60		Nivesh Rai, Hamidreza Hashempour, Yizi Xing, Bram Kruseman, Said Hamdioui: A Schematic-Based Extraction Methodology for Dislocation Defects in Analog/Mixed-Signal Devices. DFT 2011: 139-145
59		Seyab Khan, Nor Zaidi Haron, Said Hamdioui, Francky Catthoor: NBTI Monitoring and Design for Reliability in Nanoscale Circuits. DFT 2011: 68-76
58		Sandra Irobi, Zaid Al-Ars, Said Hamdioui: Memory Test Optimization for Parasitic Bit Line Coupling in SRAMs. European Test Symposium 2011: 205
57		Mottaqiallah Taouil, Said Hamdioui: Layer Redundancy Based Yield Improvement for 3D Wafer-to-Wafer Stacked Memories. European Test Symposium 2011: 45-50
56		Seyab Khan, Said Hamdioui: Modeling and mitigating NBTI in nanoscale circuits. IOLTS 2011: 1-6
55		A. J. van de Goor, Said Hamdioui, Halil Kukner: Generic, orthogonal and low-cost March Element based memory BIST. ITC 2011: 1-10
54		Nor Zaidi Haron, Said Hamdioui: Redundant Residue Number System Code for Fault-Tolerant Hybrid Memories. JETC 7(1): 4 (2011)
	2010
53		Mottaqiallah Taouil, Said Hamdioui, Kees Beenakker, Erik Jan Marinissen: Test Cost Analysis for 3D Die-to-Wafer Stacking. Asian Test Symposium 2010: 435-441
52		A. J. van de Goor, Georgi Gaydadjiev, Said Hamdioui: Memory testing with a RISC microcontroller. DATE 2010: 214-219
51		Seyab, Said Hamdioui: NBTI modeling in the framework of temperature variation. DATE 2010: 283-286
50		A. J. van de Goor, Said Hamdioui, Georgi Gaydadjiev: Using a CISC microcontroller to test embedded memories. DDECS 2010: 261-266
49		A. J. van de Goor, Christian Jung, Said Hamdioui, Georgi Gaydadjiev: Low-cost, customized and flexible SRAM MBIST engine. DDECS 2010: 382-387
48		Said Hamdioui, A. J. van de Goor: Advanced embedded memory testing: Reducing the defect per million level at lower test cost. DDECS 2010: 7
47		Seyab Khan, Said Hamdioui: Temperature dependence of NBTI induced delay. IOLTS 2010: 15-20
46		Mottaqiallah Taouil, Said Hamdioui, Jouke Verbree, Erik Jan Marinissen: On maximizing the compound yield for 3D Wafer-to-Wafer stacked ICs. ITC 2010: 183-192
45		Sandra Irobi, Zaid Al-Ars, Said Hamdioui: Detecting memory faults in the presence of bit line coupling in SRAM devices. ITC 2010: 437-446
44		Sandra Irobi, Zaid Al-Ars, Said Hamdioui: Bit line coupling memory tests for single-cell fails in SRAMs. VTS 2010: 27-32
	2009
43		Said Hamdioui: Testing Embedded Memories in the Nano-Era: Will the Existing Approaches Survive?. Asian Test Symposium 2009: 339
42		A. J. van de Goor, Said Hamdioui, Georgi Nedeltchev Gaydadjiev, Zaid Al-Ars: New Algorithms for Address Decoder Delay Faults and Bit Line Imbalance Faults. Asian Test Symposium 2009: 391-396
41		Zaid Al-Ars, Said Hamdioui: Fault Diagnosis Using Test Primitives in Random Access Memories. Asian Test Symposium 2009: 403-408
40		Nor Zaidi Haron, Said Hamdioui: Using RRNS Codes for Cluster Faults Tolerance in Hybrid Memories. DFT 2009: 85-93
39		Nor Zaidi Haron, Said Hamdioui, Sorin Cotofana: Emerging non-CMOS nanoelectronic devices - What are they?. NEMS 2009: 63-68
38		Demid Borodin, Ben H. H. Juurlink, Said Hamdioui, Stamatis Vassiliadis: Instruction-Level Fault Tolerance Configurability. Signal Processing Systems 57(1): 89-105 (2009)
	2008
37		Zaid Al-Ars, Said Hamdioui, A. J. van de Goor, Georg Mueller: Defect Oriented Testing of the Strap Problem Under Process Variations in DRAMs. ITC 2008: 1-10
36		Zaid Al-Ars, Said Hamdioui, Georgi Gaydadjiev, Stamatis Vassiliadis: Test Set Development for Cache Memory in Modern Microprocessors. IEEE Trans. VLSI Syst. 16(6): 725-732 (2008)
	2007
35		Zaid Al-Ars, Said Hamdioui, Georgi Gaydadjiev: Manifestation of Precharge Faults in High Speed DRAM Devices. DDECS 2007: 179-184
34		Said Hamdioui, Zaid Al-Ars, Javier Jiménez, Jose Calero: PPM Reduction on Embedded Memories in System on Chip. European Test Symposium 2007: 85-90
33		Zaid Al-Ars, Said Hamdioui, Georgi Gaydadjiev: Optimizing Test Length for Soft Faults in DRAM Devices. VTS 2007: 59-66
	2006
32		Zaid Al-Ars, Said Hamdioui, A. J. van de Goor: Space of DRAM fault models and corresponding testing. DATE 2006: 1252-1257
31		Zaid Al-Ars, Said Hamdioui, A. J. van de Goor, Georgi Gaydadjiev, Jörg E. Vollrath: DRAM-Specific Space of Memory Tests. ITC 2006: 1-10
30		Said Hamdioui, Zaid Al-Ars, A. J. van de Goor: Opens and Delay Faults in CMOS RAM Address Decoders. IEEE Trans. Computers 55(12): 1630-1639 (2006)
29		Zaid Al-Ars, Said Hamdioui, A. J. van de Goor, Sultan M. Al-Harbi: Influence of Bit-Line Coupling and Twisting on the Faulty Behavior of DRAMs. IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2989-2996 (2006)
	2005
28		Zaid Al-Ars, Said Hamdioui, Jörg E. Vollrath: Investigations of Faulty DRAM Behavior Using Electrical Simulation Versus an Analytical Approach. Asian Test Symposium 2005: 434-439
27		Zaid Al-Ars, Said Hamdioui, Georg Mueller, A. J. van de Goor: Framework for Fault Analysis and Test Generation in DRAMs. DATE 2005: 1020-1021
26		Said Hamdioui, John Eleazar Q. Delos Reyes: New data-background sequences and their industrial evaluation for word-oriented random-access memories. IEEE Trans. on CAD of Integrated Circuits and Systems 24(6): 892-904 (2005)
	2004
25		Said Hamdioui, John Delos Reyes, Zaid Al-Ars: Evaluation of Intra-Word Faults in Word-Oriented RAMs. Asian Test Symposium 2004: 283-288
24		A. J. van de Goor, Said Hamdioui, Rob Wadsworth: Detecting Faults in the Peripheral Circuits and an Evaluation of SRAM Tests. ITC 2004: 114-123
23		A. J. van de Goor, Said Hamdioui, Zaid Al-Ars: The Effectiveness of the Scan Test and Its New Variants. MTDT 2004: 26-31
22		Said Hamdioui, Georgi Gaydadjiev, A. J. van de Goor: The State-of-Art and Future Trends in Testing Embedded Memories. MTDT 2004: 54-59
21		Zaid Al-Ars, Said Hamdioui, A. J. van de Goor: Effects of Bit Line Coupling on the Faulty Behavior of DRAMs. VTS 2004: 117-122
20		Said Hamdioui, Zaid Al-Ars, A. J. van de Goor, Mike Rodgers: Linked faults in random access memories: concept, fault models, test algorithms, and industrial results. IEEE Trans. on CAD of Integrated Circuits and Systems 23(5): 737-757 (2004)
19		Said Hamdioui, Rob Wadsworth, John Delos Reyes, A. J. van de Goor: Memory Fault Modeling Trends: A Case Study. J. Electronic Testing 20(3): 245-255 (2004)
	2003
18		Said Hamdioui, Zaid Al-Ars, A. J. van de Goor, Mike Rodgers: March SL: A Test For All Static Linked Memory Faults. Asian Test Symposium 2003: 372-377
17		Zaid Al-Ars, Said Hamdioui, A. J. van de Goor: A Fault Primitive Based Analysis of Linked Faults in RAMs. MTDT 2003: 33-
16		Said Hamdioui, A. J. van de Goor, Mike Rodgers: Detecting Intra-Word Faults in Word-Oriented Memories. VTS 2003: 241-247
15		Said Hamdioui, Zaid Al-Ars, A. J. van de Goor, Mike Rodgers: Dynamic Faults in Random-Access-Memories: Concept, Fault Models and Tests. J. Electronic Testing 19(2): 195-205 (2003)
	2002
14		Said Hamdioui, A. J. van de Goor, Mike Rodgers: March SS: A Test for All Static Simple RAM Faults. MTDT 2002: 95-100
13		Said Hamdioui, Zaid Al-Ars, A. J. van de Goor: Testing Static and Dynamic Faults in Random Access Memories. VTS 2002: 395-400
12		Said Hamdioui, A. J. van de Goor: Efficient Tests for Realistic Faults in Dual-Port SRAMs. IEEE Trans. Computers 51(5): 460-473 (2002)
11		Said Hamdioui, A. J. van de Goor: Thorough testing of any multiport memory with linear tests. IEEE Trans. on CAD of Integrated Circuits and Systems 21(2): 217-231 (2002)
	2001
10		Said Hamdioui, A. J. van de Goor, David Eastwick, Mike Rodgers: Detecting Unique Faults in Multi-port SRAMs. Asian Test Symposium 2001: 37-42
9		Said Hamdioui, A. J. van de Goor, David Eastwick, Mike Rodgers: Realistic Fault Models and Test Procedures for Multi-Port SRAMs. MTDT 2001: 65-72
	2000
8		Said Hamdioui, A. J. van de Goor: An experimental analysis of spot defects in SRAMs: realistic fault models and tests. Asian Test Symposium 2000: 131-138
7		Said Hamdioui, A. J. van de Goor, Mike Rodgers, David Eastwick: March Tests for Realistic Faults in Two-Port Memories. MTDT 2000: 73-78
6		Said Hamdioui, A. J. van de Goor: Testing Address Decoder Faults in Two-Port Memories: Fault Models, Tests, Consequences of Port Restrictions, and Test Strategy. J. Electronic Testing 16(5): 487-498 (2000)
	1999
5		Said Hamdioui, A. J. van de Goor: March Tests for Word-Oriented Two-Port Memories. Asian Test Symposium 1999: 53-
4		Said Hamdioui, A. J. van de Goor: Port interference faults in two-port memories. ITC 1999: 1001-1010
	1998
3		Said Hamdioui, A. J. van de Goor: Consequences of Port Restriction on Testing Address Decoders in Two-Port Memories. Asian Test Symposium 1998: 340-347
2		Said Hamdioui, A. J. van de Goor: Consequences of port restrictions on testing two-port memories. ITC 1998: 63-72
1		A. J. van de Goor, Said Hamdioui: Fault Models and Tests for Two-Port Memories. VTS 1998: 401-410

Coauthor Index

1	Abdallatif S. Abu-Issa	[61]
2	Zaid Al-Ars	[13] [15] [17] [18] [20] [21] [23] [25] [27] [28] [29] [30] [31] [32] [33] [34] [35] [36] [37] [41] [42] [44] [45] [58] [63] [66] [68]
3	Sultan M. Al-Harbi	[29]
4	Ahmed Awad	[61]
5	Kees Beenakker (C. I. M. Beenakker)	[53] [69]
6	Demid Borodin	[38]
7	Jose Calero	[34]
8	Francky Catthoor	[59]
9	Sorin Cotofana (Sorin Dan Cotofana)	[39]
10	David Eastwick	[7] [9] [10]
11	Georgi Gaydadjiev (Georgi Nedeltchev Gaydadjiev)	[22] [31] [33] [35] [36] [42] [49] [50] [52]
12	A. J. van de Goor	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [27] [29] [30] [31] [32] [37] [42] [48] [49] [50] [52] [55]
13	Nor Zaidi Haron	[39] [40] [54] [59] [64] [67] [70]
14	Hamidreza Hashempour	[60]
15	Sandra Irobi (Ijeoma Sandra Irobi)	[44] [45] [58] [63] [66] [68]
16	Javier Jiménez	[34]
17	Christian Jung	[49]
18	Ben H. H. Juurlink	[38]
19	Seyab Khan	[47] [56] [59]
20	Venkataraman Krishnaswami	[68]
21	Bram Kruseman	[60]
22	Halil Kukner	[55]
23	Erik Jan Marinissen	[46] [53] [69]
24	Georg Mueller	[27] [37]
25	Nivesh Rai	[60]
26	Michel Renovell	[63]
27	John Delos Reyes	[19] [25]
28	John Eleazar Q. Delos Reyes	[26]
29	Mike Rodgers	[7] [9] [10] [14] [15] [16] [18] [20]
30	Seyab	[51]
31	Mottaqiallah Taouil	[46] [53] [57] [62] [65] [69]
32	Claude Thibeault	[66]
33	Stamatis Vassiliadis	[36] [38]
34	Jouke Verbree	[46]
35	Jörg E. Vollrath	[28] [31]
36	Rob Wadsworth	[19] [24]
37	Yizi Xing	[60]

Colors in the list of coauthors

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