Naohiro Hamada

	2012
7		Naohiro Hamada, Hiroshi Saito: Integration of Behavioral Synthesis and Floorplanning for Asynchronous Circuits with Bundled-Data Implementation. IEICE Transactions 95-C(4): 506-515 (2012)
	2011
6		Naohiro Hamada, Hiroshi Saito: Integration of behavioral synthesis and floorplanning for asynchronous circuits with bundled-data implementation. ACM Great Lakes Symposium on VLSI 2011: 157-162
5		Minoru Iizuka, Naohiro Hamada, Hiroshi Saito, Ryoichi Yamaguchi, Minoru Yoshinaga: A tool set for the design of asynchronous circuits with bundled-data implementation. ICCD 2011: 78-83
	2010
4		Hiroshi Saito, Naohiro Hamada, Tomohiro Yoneda, Takashi Nanya: A floorplan method for asynchronous circuits with bundled-data implementation on FPGAs. ISCAS 2010: 925-928
	2008
3		Naohiro Hamada, Yuuki Shiga, Hiroshi Saito, Tomohiro Yoneda, Chris J. Myers, Takashi Nanya: A behavioral synthesis method for asynchronous circuits with bundled-data implementation (Tool paper). ACSD 2008: 50-55
	2007
2		Takao Konishi, Naohiro Hamada, Hiroshi Saito: A Control Circuit Synthesis Method for Asynchronous Circuits in Bundled-Data Implementation. CIT 2007: 847-852
1		Hiroshi Saito, Naohiro Hamada, Nattha Jindapetch, Tomohiro Yoneda, Chris J. Myers, Takashi Nanya: Scheduling Methods for Asynchronous Circuits with Bundled-Data Implementations Based on the Approximation of Start Times. IEICE Transactions 90-A(12): 2790-2799 (2007)

Coauthor Index

1	Minoru Iizuka	[5]
2	Nattha Jindapetch	[1]
3	Takao Konishi	[2]
4	Chris J. Myers	[1] [3]
5	Takashi Nanya	[1] [3] [4]
6	Hiroshi Saito	[1] [2] [3] [4] [5] [6] [7]
7	Yuuki Shiga	[3]
8	Ryoichi Yamaguchi	[5]
9	Tomohiro Yoneda	[1] [3] [4]
10	Minoru Yoshinaga	[5]

Last update Thu May 31 18:55:10 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page