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| 2012 | ||
|---|---|---|
| 41 | Wei Ting Loke, Yajun Ha: A Routing Architecture for FPGAs with Dual-VT Switch Box and Logic Clusters. ARC 2012: 174-186 | |
| 40 | Wei Ting Loke, Yajun Ha: Power-aware FPGA technology mapping for programmable-VT architectures (abstract only). FPGA 2012: 268 | |
| 2011 | ||
| 39 | Wenjuan Zhang, Yajun Ha: A Hilbert curve-based delay fault characterization method for FPGAs. ISCAS 2011: 2059-2062 | |
| 2010 | ||
| 38 | Jinian Bian, Qiang Zhou, Peter Athanas, Yajun Ha, Kang Zhao: Proceedings of the International Conference on Field-Programmable Technology, FPT 2010, 8-10 December 2010, Tsinghua University, Beijing, China IEEE 2010 | |
| 37 | Heng Yu, Bharadwaj Veeravalli, Yajun Ha: Leakage-aware dynamic scheduling for real-time adaptive applications on multiprocessor systems. DAC 2010: 493-498 | |
| 36 | Amit Kumar Singh, Akash Kumar, Thambipillai Srikanthan, Yajun Ha: Mapping real-life applications on run-time reconfigurable NoC-based MPSoC on FPGA. FPT 2010: 365-368 | |
| 35 | Zhiyao Joseph Yang, Akash Kumar, Yajun Ha: An area-efficient dynamically reconfigurable Spatial Division Multiplexing network-on-chip with static throughput guarantee. FPT 2010: 389-392 | |
| 34 | Heng Yu, Yajun Ha, Bharadwaj Veeravalli: Communication-aware application mapping and scheduling for NoC-based MPSoCs. ISCAS 2010: 3232-3235 | |
| 33 | Trang T. T. Do, Thinh M. Le, Binh P. Nguyen, Yajun Ha: Performance-cost analyses software for H.264 Forward/Inverse Integer Transform. International Symposium on Rapid System Prototyping 2010: 1-7 | |
| 32 | Haiting Tian, Shakith Fernando, Hock Wei Soon, Zhang Qiang, Chunxi Zhang, Yajun Ha, Nanguang Chen: Ultra Storage-Efficient Time Digitizer for Pseudorandom Single Photon Counter Implemented on a Field-Programmable Gate Array. IEEE Trans. Biomed. Circuits and Systems 4(1): 1-10 (2010) | |
| 31 | Akash Kumar, Bart Mesman, Henk Corporaal, Yajun Ha: Iterative Probabilistic Performance Prediction for Multi-Application Multiprocessor Systems. IEEE Trans. on CAD of Integrated Circuits and Systems 29(4): 538-551 (2010) | |
| 30 | Yu Pu, Jose de Jesus Pineda de Gyvez, Henk Corporaal, Yajun Ha: An Ultra-Low-Energy Multi-Standard JPEG Co-Processor in 65 nm CMOS With Sub/Near Threshold Supply Voltage. J. Solid-State Circuits 45(3): 668-680 (2010) | |
| 2009 | ||
| 29 | Pramod Kumar Meher, Yajun Ha, Chiou-Yng Lee: An optimized design for serial-parallel finite field multiplication over GF(2m) based on all-one polynomials. ASP-DAC 2009: 210-215 | |
| 28 | Guolei Zhu, Heng Yu, Yajun Ha, Yingmin Wang: A Multi-Application Mapping Framework for Network-on-Chip Based MPSoC: An FPGA Implementation Case Study. ERSA 2009: 267-270 | |
| 27 | Rizwan Syed, Xiaolei Chen, Yajun Ha, Bharadwaj Veeravalli: sFPGA2 - A scalable GALS FPGA architecture and design methodology. FPL 2009: 314-319 | |
| 26 | Yu Pu, Jose de Jesus Pineda de Gyvez, Henk Corporaal, Yajun Ha: An ultra-low-energy/frame multi-standard JPEG co-processor in 65nm CMOS with sub/near-threshold power supply. ISSCC 2009: 146-147 | |
| 2008 | ||
| 25 | Yu Pu, Jose de Jesus Pineda de Gyvez, Henk Corporaal, Yajun Ha: Statistical noise margin estimation for sub-threshold combinational circuits. ASP-DAC 2008: 176-179 | |
| 24 | Heng Yu, Bharadwaj Veeravalli, Yajun Ha: Dynamic scheduling of imprecise-computation tasks in maximizing QoS under energy constraints for embedded systems. ASP-DAC 2008: 452-455 | |
| 23 | Hanyu Liu, Xiaolei Chen, Yajun Ha: An Area-Efficient Timing-Driven Routing Algorithm for Scalable FPGAs with Time-Multiplexed Interconnects. FCCM 2008: 275-276 | |
| 22 | Haiting Tian, Shakith Fernando, Hock Wei Soon, Yajun Ha, Nanguang Chen: Design of a high speed pseudo-random bit sequence based time resolved single photon counter on FPGA. FPL 2008: 583-586 | |
| 21 | Hanyu Liu, Xiaolei Chen, Yajun Ha: An architecture and timing-driven routing algorithm for area-efficient FPGAs with time-multiplexed interconnects. FPL 2008: 615-618 | |
| 20 | Fujie Wong, Yajun Ha: A low overhead fault tolerant FPGA with new connection box. FPL 2008: 643-646 | |
| 19 | Shakith Fernando, Xiaolei Chen, Yajun Ha: sFPGA - A scalable switch based FPGA architecture and design methodology. FPL 2008: 95-100 | |
| 18 | Akash Kumar, Shakith Fernando, Yajun Ha, Bart Mesman, Henk Corporaal: Multiprocessor systems synthesis for multiple use-cases of multiple applications on FPGA. ACM Trans. Design Autom. Electr. Syst. 13(3): (2008) | |
| 17 | Jenn-Yue Teo, Yajun Ha, Chen-Khong Tham: Interference-Minimized Multipath Routing with Congestion Control in Wireless Sensor Network for High-Rate Streaming. IEEE Trans. Mob. Comput. 7(9): 1124-1137 (2008) | |
| 16 | Akash Kumar, Bart Mesman, Bart D. Theelen, Henk Corporaal, Yajun Ha: Analyzing composability of applications on MPSoC platforms. Journal of Systems Architecture - Embedded Systems Design 54(3-4): 369-383 (2008) | |
| 2007 | ||
| 15 | Akash Kumar, Bart Mesman, Henk Corporaal, Bart D. Theelen, Yajun Ha: A Probabilistic Approach to Model Resource Contention for Performance Estimation of Multi-featured Media Devices. DAC 2007: 726-731 | |
| 14 | Chee Sing Lee, Wei Ting Loke, Wenjuan Zhang, Yajun Ha: Fast and Accurate Interval-Based Timing Estimator for Variability-Aware FPGA Physical Synthesis Tools. FPL 2007: 279-284 | |
| 13 | Akash Kumar, Shakith Fernando, Yajun Ha, Bart Mesman, Henk Corporaal: Multi-processor System-level Synthesis for Multiple Applications on Platform FPGA. FPL 2007: 92-97 | |
| 12 | Yu Pu, Jose de Jesus Pineda de Gyvez, Henk Corporaal, Yajun Ha: Vt balancing and device sizing towards high yield of sub-threshold static logic gates. ISLPED 2007: 355-358 | |
| 2006 | ||
| 11 | Yu Pu, Yajun Ha: An automated, efficient and static bit-width optimization methodology towards maximum bit-width-to-error tradeoff with affine arithmetic model. ASP-DAC 2006: 886-891 | |
| 10 | Akash Kumar, Bart Mesman, Henk Corporaal, Jef L. van Meerbergen, Yajun Ha: Global Analysis of Resource Arbitration for MPSoC. DSD 2006: 71-78 | |
| 9 | Akash Kumar, Bart Mesman, Bart D. Theelen, Henk Corporaal, Yajun Ha: Resource Manager for Non-preemptive Heterogeneous Multiprocessor System-on-chip. ESTImedia 2006: 33-38 | |
| 2005 | ||
| 8 | Shakith Fernando, Yajun Ha: Design of Networked Reconfigurable Encryption Engine. FCCM 2005: 285-286 | |
| 7 | Yung Han Tan, Arun Krishnan Thampi, Daley Joseph Sebastian, Yajun Ha: Design of Seamless Protocol Switching Layer for Voice Over Internet Protocol (Voip) That Switches Between Bluetooth and Ieee 802.11. International Journal of Software Engineering and Knowledge Engineering 15(2): 271-278 (2005) | |
| 2002 | ||
| 6 | Yajun Ha, Radovan Hipik, Serge Vernalde, Diederik Verkest, Marc Engels, Rudy Lauwereins, Hugo De Man: Adding Hardware Support to the HotSpot Virtual Machine for Domain Specific Applications. FPL 2002: 1135-1138 | |
| 5 | Yajun Ha, Serge Vernalde, Patrick Schaumont, Marc Engels, Rudy Lauwereins, Hugo De Man: Building a Virtual Framework for Networked Reconfigurable Hardware and Software Objects. The Journal of Supercomputing 21(2): 131-144 (2002) | |
| 2001 | ||
| 4 | Yajun Ha, Geert Vanmeerbeeck, Patrick Schaumont, Serge Vernalde, Marc Engels, Rudy Lauwereins, Hugo De Man: Virtual Java/FPGA interface for networked reconfiguration. ASP-DAC 2001: 558-563 | |
| 3 | Yajun Ha, Bingfeng Mei, Patrick Schaumont, Serge Vernalde, Rudy Lauwereins, Hugo De Man: Development of a Design Framework for Platform-Independent Networked Reconfiguration of Software and Hardware. FPL 2001: 264-274 | |
| 2000 | ||
| 2 | Yajun Ha, Patrick Schaumont, Marc Engels, Serge Vernalde, Freddy Potargent, Luc Rijnders, Hugo De Man: A Hardware Virtual Machine for the Networked Reconfiguration. IEEE International Workshop on Rapid System Prototyping 2000: 194-199 | |
| 1 | Yajun Ha, Serge Vernalde, Patrick Schaumont, Marc Engels, Hugo De Man: Building a Virtual Framework for Networked Reconfigurable Hardware and Software Objects. PDPTA 2000 | |
Colors in the list of coauthors
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