José Pineda de Gyvez

	2012
58		Hamid Reza Pourshaghaghi, Hamed Fatemi, José Pineda de Gyvez: Sliding-Mode Control to Compensate PVT Variations in dual core systems. DATE 2012: 1048-1053
57		Maurice Meijer, José Pineda de Gyvez: Body-Bias-Driven Design Strategy for Area- and Performance-Efficient CMOS Circuits. IEEE Trans. VLSI Syst. 20(1): 42-51 (2012)
56		Amir Zjajo, Manuel J. Barragan Asian, José Pineda de Gyvez: Digital Adaptive Calibration of Multi-Step Analog to Digital Converters. J. Low Power Electronics 8(2): 182-196 (2012)
	2011
55		Bo Liu, Hamid Reza Pourshaghaghi, Sebastian M. Londono, José Pineda de Gyvez: Process Variation Reduction for CMOS Logic Operating at Sub-threshold Supply Voltage. DSD 2011: 135-139
54		Amir Zjajo, José Pineda de Gyvez: A 1.2v 55mW 12bits self-calibrated dual-residue analog to digital converter in 90 nm CMOs. ISLPED 2011: 187-192
53		Amir Zjajo, Qin Tang, Michel Berkelaar, José Pineda de Gyvez, Alessandro Di Bucchianico, Nick van der Meijs: Stochastic Analysis of Deep-Submicrometer CMOS Process for Reliable Circuits Designs. IEEE Trans. on Circuits and Systems 58-I(1): 164-175 (2011)
	2010
52		Hamid Reza Pourshaghaghi, José Pineda de Gyvez: Power-performance optimization using fuzzy control of simultaneous supply voltage and body biasing scaling. ICECS 2010: 281-284
51		Maurice Meijer, José Pineda de Gyvez, Ben Kup, Bert van Uden, Peter Bastiaansen, Marco Lammers, Maarten Vertregt: A forward body bias generator for digital CMOS circuits with supply voltage scaling. ISCAS 2010: 2482-2485
50		Maurice Meijer, José Pineda de Gyvez: Body bias driven design synthesis for optimum performance per area. ISQED 2010: 472-477
49		Maurice Meijer, José Pineda de Gyvez, Ajay Kapoor: Ultra-Low-Power Digital Design with Body Biasing for Low Area and Performance-Efficient Operation. J. Low Power Electronics 6(4): 521-532 (2010)
	2009
48		Hamid Reza Pourshaghaghi, José Pineda de Gyvez: Dynamic voltage scaling based on supply current tracking using fuzzy Logic controller. ICECS 2009: 779-782
47		Sebastian M. Londono, José Pineda de Gyvez: An energy-aware multiplier based on a Configurable-Reuse of points design methodology. ICECS 2009: 89-92
46		Amir Zjajo, José Pineda de Gyvez: Analog Automatic Test Pattern Generation for Quasi-Static Structural Test. IEEE Trans. VLSI Syst. 17(10): 1383-1391 (2009)
	2008
45		Amir Zjajo, José Pineda de Gyvez: Diagnostic Analysis of Static Errors in Multi-Step Analog to Digital Converters. DATE 2008: 74-79
44		Amir Zjajo, Shaji Krishnan, José Pineda de Gyvez: Efficient Estimation of Die-Level Process Parameter Variations via the EM-Algorithm. DDECS 2008: 287-292
43		Amir Zjajo, José Pineda de Gyvez: Calibration and Debugging of Multi-step Analog to Digital Converters. DELTA 2008: 512-515
	2007
42		Amir Zjajo, Manuel J. Barragan Asian, José Pineda de Gyvez: Interactive presentation: BIST method for die-level process parameter variation monitoring in analog/mixed-signal integrated circuits. DATE 2007: 1301-1306
41		Sandeep Kumar Goel, Maurice Meijer, José Pineda de Gyvez: Efficient testing and diagnosis of faulty power switches in SOCs. IET Computers & Digital Techniques 1(3): 230-236 (2007)
	2006
40		Sandeep Kumar Goel, Maurice Meijer, José Pineda de Gyvez: Testing and Diagnosis of Power Switches in SOCs. European Test Symposium 2006: 145-150
39		Amir Zjajo, José Pineda de Gyvez, Guido Gronthoud: Structural Fault Modeling and Fault Detection Through Neyman-Pearson Decision Criteria for Analog Integrated Circuits. J. Electronic Testing 22(4-6): 399-409 (2006)
38		Josep Rius, Maurice Meijer, José Pineda de Gyvez: An Activity Monitor for Power/Performance Tuning of CMOS Digital Circuits. J. Low Power Electronics 2(1): 80-86 (2006)
	2005
37		Maurice Meijer, Francesco Pessolano, José Pineda de Gyvez: Limits to performance spread tuning using adaptive voltage and body biasing. ISCAS (1) 2005: 5-8
36		Maurice Meijer, Francesco Pessolano, José Pineda de Gyvez: Glitch-free discretely programmable clock generation on chip. ISCAS (2) 2005: 1839-1842
35		Maurice Meijer, José Pineda de Gyvez, Ralph Otten: On-chip digital power supply control for system-on-chip applications. ISLPED 2005: 311-314
34		Andrei Pavlov, Mohamed Azimane, José Pineda de Gyvez, Manoj Sachdev: Word line pulsing technique for stability fault detection in SRAM cells. ITC 2005: 10
33		Amir Zjajo, Hendrik J. Bergveld, Rodger Schuttert, José Pineda de Gyvez: Power-scan chain: design for analog testability. ITC 2005: 8
32		Estella Silva, José Pineda de Gyvez, Guido Gronthoud: Functional vs. multi-VDD testing of RF circuits. ITC 2005: 9
31		Josep Rius, José Pineda de Gyvez, Maurice Meijer: An Activity Monitor for Power/Performance Tuning of CMOS Digital Circuits. PATMOS 2005: 187-196
30		José Pineda de Gyvez, Guido Gronthoud, Rashid Amine: Multi-VDD Testing for Analog Circuits. J. Electronic Testing 21(3): 311-322 (2005)
	2004
29		Rohini Krishnan, José Pineda de Gyvez, Martijn T. Bennebroek: Low energy FPGA interconnect design. ACM Great Lakes Symposium on VLSI 2004: 393-396
28		Josep Rius Vázquez, José Pineda de Gyvez: Power Supply Noise Monitor for Signal Integrity Faults. DATE 2004: 1406-1407
27		Rohini Krishnan, José Pineda de Gyvez, Martijn T. Bennebroek: Low energy FPGA interconnect design. FPGA 2004: 255
26		Maurice Meijer, Francesco Pessolano, José Pineda de Gyvez: Technology exploration for adaptive power and frequency scaling in 90nm CMOS. ISLPED 2004: 14-19
25		Andrei Pavlov, Manoj Sachdev, José Pineda de Gyvez: AN SRAM Weak Cell Fault Model and a DFT Technique with a Programmable Detection Threshold. ITC 2004: 1006-1015
24		José Pineda de Gyvez, Guido Gronthoud, Cristiano Cenci, Martin Posch, Thomas Burger, Manfred Koller: Power Supply Ramping for Quasi-static Testing of PLLs. ITC 2004: 980-987
23		Rohini Krishnan, José Pineda de Gyvez: Low Energy Switch Block For FPGAs. VLSI Design 2004: 209-214
22		Josep Rius Vázquez, José Pineda de Gyvez: Built-in Current Sensor for ?I{DDQ} Testing of Deep Submicron Digital CMOS ICs. VTS 2004: 53-58
	2003
21		Rohini Krishnan, José Pineda de Gyvez, Harry J. M. Veendrick: Encoded-Low Swing Technique for Ultra Low Power Interconnect. FPL 2003: 240-251
20		José Pineda de Gyvez, Guido Gronthoud, Rashid Amine: VDD Ramp Testing for RF Circuits. ITC 2003: 651-658
19		Antonio F. Mondragón-Torres, Terry Mayhugh Jr., José Pineda de Gyvez, José Silva-Martínez, Edgar Sánchez-Sinencio: An Analog Integrated Circuit Design Laboratory. MSE 2003: 91-92
18		José Pineda de Gyvez, Rosa Rodríguez-Montañés: Threshold Voltage Mismatch (DeltaVT) Fault Modeling. VTS 2003: 145-150
17		Phillip Christie, José Pineda de Gyvez: Prelayout interconnect yield prediction. IEEE Trans. VLSI Syst. 11(1): 55-59 (2003)
	2002
16		Rosa Rodríguez-Montañés, Paul Volf, José Pineda de Gyvez: Resistance Characterization for Weak Open Defects. IEEE Design & Test of Computers 19(5): 18-26 (2002)
	2001
15		José Pineda de Gyvez: Yield modeling and BEOL fundamentals. SLIP 2001: 135-163
14		Phillip Christie, José Pineda de Gyvez: Pre-layout prediction of interconnect manufacturability. SLIP 2001: 167-173
13		José Pineda de Gyvez, Eric van de Wetering: Average Leakage Current Estimation of CMOS Logic Circuits. VTS 2001: 375-379
	2000
12		Madhuban Kishor, José Pineda de Gyvez: Threshold Voltage and Power-Supply Tolerance of CMOS Logic Design Families. DFT 2000: 349-357
	1999
11		O. A. Gonzalez, Gunhee Han, José Pineda de Gyvez, Edgar Sánchez-Sinencio: CMOS cryptosystem using a Lorenz chaotic oscillator. ISCAS (5) 1999: 442-445
10		A. Dornbusch, José Pineda de Gyvez: Chaotic generation of PN sequences: a VLSI implementation. ISCAS (5) 1999: 454-457
	1998
9		Lei Wang, José Pineda de Gyvez, Edgar Sánchez-Sinencio: Time multiplexed color image processing based on a CNN with cell-state outputs. IEEE Trans. VLSI Syst. 6(2): 314-322 (1998)
	1996
8		Apollo Q. Fong, Ajay Kanji, José Pineda de Gyvez: Time-Multiplexing Scheme for Cellular Neural Networks Based Image Processing. Real-Time Imaging 2(4): 231-239 (1996)
	1995
7		Apollo Q. Fong, Ajay Kanji, Edgar Sánchez-Sinencio, José Pineda de Gyvez: A Universal Interface Between PC and Neural Networks Hardware. ISCAS 1995: 1169-1172
6		Oscar Moreira-Tamayo, José Pineda de Gyvez: Time Domain Analog Wavelet Transform in Real-Time. ISCAS 1995: 1640-1643
	1994
5		Chi-Chien Lee, José Pineda de Gyvez: Single-Layer CNN Simulator. ISCAS 1994: 217-220
4		John Willis, José Pineda de Gyvez: Behavioral Testing of Cellular Neural Networks. ISCAS 1994: 229-232
3		Chi-Chien Lee, José Pineda de Gyvez: Time-Mulitplexing CNN Simulator. ISCAS 1994: 407-410
	1992
2		José Pineda de Gyvez, Chennian Di: IC defect sensitivity for footprint-type spot defects. IEEE Trans. on CAD of Integrated Circuits and Systems 11(5): 638-658 (1992)
	1989
1		José Pineda de Gyvez, Jochen A. G. Jess: On the design and implementation of a wafer yield editor. IEEE Trans. on CAD of Integrated Circuits and Systems 8(8): 920-925 (1989)

Coauthor Index

1	Rashid Amine	[20] [30]
2	Manuel J. Barragan Asian	[42] [56]
3	Mohamed Azimane	[34]
4	Peter Bastiaansen	[51]
5	Martijn T. Bennebroek	[27] [29]
6	Hendrik J. Bergveld	[33]
7	Michel Berkelaar	[53]
8	Alessandro Di Bucchianico	[53]
9	Thomas Burger	[24]
10	Cristiano Cenci	[24]
11	Phillip Christie	[14] [17]
12	Chennian Di	[2]
13	A. Dornbusch	[10]
14	Hamed Fatemi	[58]
15	Apollo Q. Fong	[7] [8]
16	Sandeep Kumar Goel	[40] [41]
17	O. A. Gonzalez	[11]
18	Guido Gronthoud	[20] [24] [30] [32] [39]
19	Gunhee Han	[11]
20	Jochen A. G. Jess	[1]
21	Ajay Kanji	[7] [8]
22	Ajay Kapoor	[49]
23	Madhuban Kishor	[12]
24	Manfred Koller	[24]
25	Rohini Krishnan	[21] [23] [27] [29]
26	Shaji Krishnan	[44]
27	Ben Kup	[51]
28	Marco Lammers	[51]
29	Chi-Chien Lee	[3] [5]
30	Bo Liu	[55]
31	Sebastian M. Londono	[47] [55]
32	Terry Mayhugh Jr.	[19]
33	Maurice Meijer	[26] [31] [35] [36] [37] [38] [40] [41] [49] [50] [51] [57]
34	N. P. van der Meijs (Nick van der Meijs)	[53]
35	Antonio F. Mondragón-Torres	[19]
36	Oscar Moreira-Tamayo	[6]
37	Ralph Otten	[35]
38	Andrei Pavlov	[25] [34]
39	Francesco Pessolano	[26] [36] [37]
40	Martin Posch	[24]
41	Hamid Reza Pourshaghaghi	[48] [52] [55] [58]
42	Rosa Rodríguez-Montañés	[16] [18]
43	Manoj Sachdev	[25] [34]
44	Edgar Sánchez-Sinencio	[7] [9] [11] [19]
45	Rodger Schuttert	[33]
46	Estella Silva	[32]
47	José Silva-Martínez	[19]
48	Qin Tang	[53]
49	Bert van Uden	[51]
50	Josep Rius Vázquez (Josep Rius)	[22] [28] [31] [38]
51	Harry J. M. Veendrick	[21]
52	Maarten Vertregt	[51]
53	Paul Volf	[16]
54	Lei Wang	[9]
55	Eric van de Wetering	[13]
56	John Willis	[4]
57	Amir Zjajo	[33] [39] [42] [43] [44] [45] [46] [53] [54] [56]

Colors in the list of coauthors

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