Zvika Guz

	2010
9		Zvika Guz, Oved Itzhak, Idit Keidar, Avinoam Kolodny, Avi Mendelson, Uri C. Weiser: Threads vs. caches: Modeling the behavior of parallel workloads. ICCD 2010: 274-281
	2009
8		Haggai Eran, Ohad Lutzky, Zvika Guz, Idit Keidar: Transactifying Apache's cache module. SYSTOR 2009: 2
7		Zvika Guz, Evgeny Bolotin, Idit Keidar, Avinoam Kolodny, Avi Mendelson, Uri C. Weiser: Many-Core vs. Many-Thread Machines: Stay Away From the Valley. Computer Architecture Letters 8(1): 25-28 (2009)
	2008
6		Zvika Guz, Idit Keidar, Avinoam Kolodny, Uri C. Weiser: Utilizing shared data in chip multiprocessors with the nahalal architecture. SPAA 2008: 1-10
5		Zvika Guz: Review of SPAA'08. SIGACT News 39(4): 66-68 (2008)
	2007
4		Evgeny Bolotin, Zvika Guz, Israel Cidon, Ran Ginosar, Avinoam Kolodny: The Power of Priority: NoC Based Distributed Cache Coherency. NOCS 2007: 117-126
3		Zvika Guz, Idit Keidar, Avinoam Kolodny, Uri C. Weiser: Nahalal: Cache Organization for Chip Multiprocessors. Computer Architecture Letters 6(1): 21-24 (2007)
2		Zvika Guz, Isask'har Walter, Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny: Network Delays and Link Capacities in Application-Specific Wormhole NoCs. VLSI Design 2007: (2007)
	2006
1		Zvika Guz, Isask'har Walter, Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny: Efficient link capacity and QoS design for network-on-chip. DATE 2006: 9-14

Coauthor Index

1	Evgeny Bolotin	[1] [2] [4] [7]
2	Israel Cidon	[1] [2] [4]
3	Haggai Eran	[8]
4	Ran Ginosar	[1] [2] [4]
5	Oved Itzhak	[9]
6	Idit Keidar	[3] [6] [7] [8] [9]
7	Avinoam Kolodny	[1] [2] [3] [4] [6] [7] [9]
8	Ohad Lutzky	[8]
9	Avi Mendelson	[7] [9]
10	Isask'har Walter	[1] [2]
11	Uri C. Weiser	[3] [6] [7] [9]

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