 | 2012 |
| 24 |  | Curtis Andrus,
Matthew R. Guthaus:
Lithography-aware layout compaction.
ACM Great Lakes Symposium on VLSI 2012: 147-152 |
| 23 |  | Xuchu Hu,
Walter James Condley,
Matthew R. Guthaus:
Library-aware resonant clock synthesis (LARCS).
DAC 2012: 145-150 |
| 22 |  | Jeren Samandari-Rad,
Matthew R. Guthaus,
Richard Hughey:
VAR-TX: A variability-aware SRAM model for predicting the optimum architecture to achieve minimum access-time for yield enhancement in nano-scaled CMOS.
ISQED 2012: 506-515 |
| 2011 |
| 21 |  | Xuchu Hu,
Matthew R. Guthaus:
Clock tree optimization for Electromagnetic Compatibility (EMC).
ASP-DAC 2011: 184-189 |
| 20 |  | Seokjoong Kim,
Matthew R. Guthaus:
Leakage-aware redundancy for reliable sub-threshold memories.
DAC 2011: 435-440 |
| 19 |  | Xuchu Hu,
Matthew R. Guthaus:
Distributed Resonant clOCK grid Synthesis (ROCKS).
DAC 2011: 516-521 |
| 18 |  | Walter James Condley,
Xuchu Hu,
Matthew R. Guthaus:
A methodology for local resonant clock synthesis using LC-assisted local clock buffers.
ICCAD 2011: 503-506 |
| 17 |  | Seokjoong Kim,
Matthew R. Guthaus:
Low-power multiple-bit upset tolerant memory optimization.
ICCAD 2011: 577-581 |
| 16 |  | Matthew R. Guthaus:
Distributed LC resonant clock tree synthesis.
ISCAS 2011: 1215-1218 |
| 15 |  | Sheldon Logan,
Matthew R. Guthaus:
Package-chip co-design to increase flip-chip C4 reliability.
ISQED 2011: 553-558 |
| 14 |  | Seokjoong Kim,
Matthew R. Guthaus:
SNM-aware power reduction and reliability improvement in 45nm SRAMs.
VLSI-SoC 2011: 204-207 |
| 2010 |
| 13 |  | Matthew R. Guthaus,
Gustavo Wilke,
Ricardo Reis:
Non-uniform clock mesh optimization with linear programming buffer insertion.
DAC 2010: 74-79 |
| 12 |  | Derek Chan,
Matthew R. Guthaus:
Analysis of power supply induced jitter in actively de-skewed multi-core systems.
ISQED 2010: 785-790 |
| 11 |  | Walter James Condley,
Xuchu Hu,
Matthew R. Guthaus:
Analysis of high-performance clock networks with RLC and transmission line effects.
SLIP 2010: 51-58 |
| 2009 |
| 10 |  | Michael Brown,
Cyrus Bazeghi,
Matthew R. Guthaus,
Jose Renau:
Measuring and modeling variabilityusing low-cost FPGAs.
FPGA 2009: 286 |
| 9 |  | Keven L. Woo,
Matthew R. Guthaus:
Fault-tolerant synthesis using non-uniform redundancy.
ICCD 2009: 213-218 |
| 2008 |
| 8 |  | Matthew R. Guthaus,
Dennis Sylvester,
Richard B. Brown:
Clock tree synthesis with data-path sensitivity matching.
ASP-DAC 2008: 498-503 |
| 2006 |
| 7 |  | Matthew R. Guthaus,
Dennis Sylvester,
Richard B. Brown:
Process-induced skew reduction in nominal zero-skew clock trees.
ASP-DAC 2006: 84-89 |
| 6 |  | Matthew R. Guthaus,
Dennis Sylvester,
Richard B. Brown:
Clock buffer and wire sizing using sequential programming.
DAC 2006: 1041-1046 |
| 2005 |
| 5 |  | Matthew R. Guthaus,
Natesan Venkateswaran,
Vladimir Zolotov,
Dennis Sylvester,
Richard B. Brown:
Optimization objectives and models of variation for statistical gate sizing.
ACM Great Lakes Symposium on VLSI 2005: 313-316 |
| 4 |  | Matthew R. Guthaus,
Natesan Venkateswaran,
Chandu Visweswariah,
Vladimir Zolotov:
Gate sizing using incremental parameterized statistical timing analysis.
ICCAD 2005: 1029-1036 |
| 3 |  | Rajiv A. Ravindran,
Robert M. Senger,
Eric D. Marsman,
Ganesh S. Dasika,
Matthew R. Guthaus,
Scott A. Mahlke,
Richard B. Brown:
Partitioning Variables across Register Windows to Reduce Spill Code in a Low-Power Processor.
IEEE Trans. Computers 54(8): 998-1012 (2005) |
| 2003 |
| 2 |  | Rajiv A. Ravindran,
Robert M. Senger,
Eric D. Marsman,
Ganesh S. Dasika,
Matthew R. Guthaus,
Scott A. Mahlke,
Richard B. Brown:
Increasing the number of effective registers in a low-power processor using a windowed register file.
CASES 2003: 125-136 |
| 1 |  | Robert M. Senger,
Eric D. Marsman,
Michael S. McCorquodale,
Fadi H. Gebara,
Keith L. Kraver,
Matthew R. Guthaus,
Richard B. Brown:
A 16-bit mixed-signal microsystem with integrated CMOS-MEMS clock reference.
DAC 2003: 520-525 |