 | 2012 |
|---|
| 7 |       | Subhanshu Gupta,
Daibashish Gangopadhyay,
Hasnain Lakdawala,
Jacques C. Rudell,
David J. Allstot:
A 0.8-2 GHz Fully-Integrated QPLL-Timed Direct-RF-Sampling Bandpass $\Sigma \Delta$ ADC in 0.13 $\mu$m CMOS.
J. Solid-State Circuits 47(5): 1141-1153 (2012) |
| 2011 |
|---|
| 6 | | Subhanshu Gupta,
Yi Tang,
Kuang-Wei Cheng,
Jeyanandh Paramesh,
David J. Allstot:
Multi-rate polyphase DSP and LMS calibration schemes for oversampled data conversion systems.
ICASSP 2011: 1585-1588 |
| 2010 |
|---|
| 5 | | Subhanshu Gupta,
Daibashish Gangopadhyay,
David J. Allstot:
A Mode-I/Mode-III UWB LNA with programmable gain and 20 dB WLAN blocker rejection in 130nm CMOS.
ISCAS 2010: 1093-1096 |
| 2008 |
|---|
| 4 | | Subhanshu Gupta,
Yi Tang,
David J. Allstot,
Jeyanandh Paramesh:
Hybrid modeling techniques for low OSR cascade continuous-time SigmaDelta modulators.
ISCAS 2008: 2414-2417 |
| 3 | | Yi Tang,
Kuang-Wei Cheng,
Subhanshu Gupta,
Jeyanandh Paramesh,
David J. Allstot:
Cascaded Complex ADCs With Adaptive Digital Calibration for I/Q Mismatch.
IEEE Trans. on Circuits and Systems 55-I(3): 817-827 (2008) |
| 2007 |
|---|
| 2 | | Yi Tang,
Subhanshu Gupta,
Jeyanandh Paramesh,
David J. Allstot:
A Digital-Summing Feedforward Sigma-Delta Modulator and its Application to a Cascade ADC.
ISCAS 2007: 485-488 |
| 2005 |
|---|
| 1 | | K. M. Naegle,
Subhanshu Gupta,
David J. Allstot:
Design considerations for a 10 GHz CMOS transmit-receive switch.
ISCAS (3) 2005: 2104-2107 |
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