Sandeep K. Gupta

	2012
125		Hsunwei Hsuing, Byeongju Cha, Sandeep K. Gupta: Salvaging chips with caches beyond repair. DATE 2012: 1263-1268
124		Mohammad Mirza-Aghatabar, Melvin A. Breuer, Sandeep K. Gupta, Shahin Nazarian: Theory of redundancy for logic circuits to maximize yield/area. ISQED 2012: 663-671
	2011
123		Jae Chul Cha, Sandeep K. Gupta: Yield-per-Area Optimization for 6T-SRAMs Using an Integrated Approach to Exploit Spares and ECC to Efficiently Combat High Defect and Soft-Error Rates. Asian Test Symposium 2011: 126-135
122		Prasanjeet Das, Sandeep K. Gupta: On Generating Vectors for Accurate Post-Silicon Delay Characterization. Asian Test Symposium 2011: 251-260
121		Doochul Shin, Sandeep K. Gupta: A new circuit simplification method for error tolerant applications. DATE 2011: 1566-1571
	2010
120		Mohammad Mirza-Aghatabar, Melvin A. Breuer, Sandeep K. Gupta: HYPER: A Heuristic for Yield/Area imProvEment Using Redundancy in SoC. Asian Test Symposium 2010: 249-254
119		Mohammad Mirza-Aghatabar, Melvin A. Breuer, Sandeep K. Gupta: Algorithms to maximize yield and enhance yield/area of pipeline circuitry by insertion of switches and redundant modules. DATE 2010: 1249-1254
118		Doochul Shin, Sandeep K. Gupta: Approximate logic synthesis for error tolerant applications. DATE 2010: 957-960
117		Kun Young Chung, Sandeep K. Gupta: Design and test of latch-based circuits to maximize performance, yield, and delay test quality. ITC 2010: 94-103
	2009
116		Mohammad Mirza-Aghatabar, Melvin A. Breuer, Sandeep K. Gupta: SIRUP: Switch Insertion in RedUndant Pipeline Structures for Yield and Yield/Area Improvement. Asian Test Symposium 2009: 193-199
115		Tong-Yu Hsieh, Melvin A. Breuer, Murali Annavaram, Sandeep K. Gupta, Kuen-Jong Lee: Tolerance of performance degrading faults for effective yield improvement. ITC 2009: 1-10
114		Kun Young Chung, Sandeep K. Gupta: Efficient Scheduling of Path Delay Tests for Latch-Based Circuits. VTS 2009: 103-110
113		Zhigang Jiang, Sandeep K. Gupta: Threshold Testing: Improving Yield for Nanoscale VLSI. IEEE Trans. on CAD of Integrated Circuits and Systems 28(12): 1883-1895 (2009)
	2008
112		Jae Chul Cha, Sandeep K. Gupta: Matrix Inversion on a PIM (Processor-in-Memory). CSSE (3) 2008: 419-422
111		Jae Chul Cha, Sandeep K. Gupta: Characterization of granularity and redundancy for SRAMs for optimal yield-per-area. ICCD 2008: 219-226
110		Jae Chul Cha, Sandeep K. Gupta: Data Partitioning and Placement Schemes for Matrix Multiplications on a PIM Architecture. ISPDC 2008: 309-316
109		I-De Huang, Yi-Shing Chang, Suriyaprakash Natarajan, Ramesh Sharma, Sandeep K. Gupta: On Accelerating Path Delay Fault Simulation of Long Test Sequences. ITC 2008: 1-9
108		I-De Huang, Yi-Shing Chang, Sandeep K. Gupta, Sreejit Chakravarty: An Industrial Case Study of Sticky Path-Delay Faults. VTS 2008: 395-402
107		Jung-Yup Kang, Sandeep K. Gupta, Jean-Luc Gaudiot: An Efficient Data-Distribution Mechanism in a Processor-In-Memory (PIM) Architecture Applied to Motion Estimation. IEEE Trans. Computers 57(3): 375-388 (2008)
	2007
106		Hugo Cheung, Sandeep K. Gupta: Accurate modeling and fault simulation of Byzantine resistive bridges. ICCD 2007: 347-353
105		Shideh Shahidi, Sandeep K. Gupta: ERTG: A test generator for error-rate testing. ITC 2007: 1-10
	2006
104		Shahin Nazarian, Massoud Pedram, Sandeep K. Gupta, Melvin A. Breuer: STAX: statistical crosstalk target set compaction. DATE Designers' Forum 2006: 172-177
103		Shideh Shahidi, Sandeep K. Gupta: Estimating Error Rate during Self-Test via One's Counting. ITC 2006: 1-9
102		Kun Young Chung, Sandeep K. Gupta: Low-Cost Scan-Based Delay Testing of Latch-Based Circuits with Time Borrowing. VTS 2006: 8-15
101		Seongmoon Wang, Sandeep K. Gupta: LT-RTPG: a new test-per-scan BIST TPG for low switching activity. IEEE Trans. on CAD of Integrated Circuits and Systems 25(8): 1565-1574 (2006)
	2005
100		Wichian Sirisaengtaksin, Sandeep K. Gupta: A Methodology to Compute Bounds on Crosstalk Effects in Arbitrary Interconnects. Asian Test Symposium 2005: 112-119
99		I-De Huang, Sandeep K. Gupta: Selection of Paths for Delay Testing. Asian Test Symposium 2005: 208-215
98		Zhigang Jiang, Sandeep K. Gupta: Threshold testing: Covering bridging and other realistic faults. Asian Test Symposium 2005: 390-397
97		Shahdad Irajpour, Sandeep K. Gupta, Melvin A. Breuer: Multiple tests for each gate delay fault: higher coverage and lower test application cost. ITC 2005: 9
	2004
96		Melvin A. Breuer, Sandeep K. Gupta, Shahin Nazarian: Efficient Identification of Crosstalk Induced Slowdown Targets. Asian Test Symposium 2004: 124-131
95		Wichian Sirisaengtaksin, Sandeep K. Gupta: Modeling and Testing Crosstalk Faults in Inter-Core Interconnects that Include Tri-State and Bi-Directional Nets. Asian Test Symposium 2004: 132-139
94		Lei Wang, Sandeep K. Gupta, Melvin A. Breuer: Modeling and Simulation for Crosstalk Aggravated by Weak-Bridge Defects between On-Chip Interconnects. Asian Test Symposium 2004: 440-447
93		Shahdad Irajpour, Sandeep K. Gupta, Melvin A. Breuer: Timing-Independent Testing of Crosstalk in the Presence of Delay Producing Defects Using Surrogate Fault Models. ITC 2004: 1024-1033
92		Md. Saffat Quasem, Sandeep K. Gupta: Designing Reconfigurable Multiple Scan Chains for Systems-on-Chip. VTS 2004: 367-376
91		Melvin A. Breuer, Sandeep K. Gupta, T. M. Mak: Defect and Error Tolerance in the Presence of Massive Numbers of Defects. IEEE Design & Test of Computers 21(3): 216-227 (2004)
	2003
90		Arani Sinha, Sandeep K. Gupta, Melvin A. Breuer: An Enhanced Test Generator for Capacitance Induced Crosstalk Delay Faults. Asian Test Symposium 2003: 174-177
89		Zhigang Jiang, Sandeep K. Gupta: A Test Generation Approach for Systems-on-Chip that Use Intellectual Property Cores. Asian Test Symposium 2003: 278-283
88		Md. Saffat Quasem, Sandeep K. Gupta: Designing Multiple Scan Chains for Systems-on-Chip. Asian Test Symposium 2003: 424-427
87		Kun Young Chung, Sandeep K. Gupta: Structural Delay Testing of Latch-based High-speed Pipelines with Time Borrowing. ITC 2003: 1089-1097
86		Yi-Shing Chang, Sandeep K. Gupta, Melvin A. Breuer: Test Generation for Maximizing Ground Bounce Considering Circuit Delay. VTS 2003: 151-157
85		Nabil M. Abdulrazzaq, Sandeep K. Gupta: Path-Delay Fault Simulation for Circuits with Large Numbers of Paths for Very Large Test Sets. VTS 2003: 186-196
84		Sultan M. Al-Harbi, Sandeep K. Gupta: Generating Complete and Optimal March Tests for Linked Faults in Memories. VTS 2003: 254-266
83		Shahdad Irajpour, Shahin Nazarian, Lei Wang, Sandeep K. Gupta, Melvin A. Breuer: Analyzing Crosstalk in the Presence of Weak Bridge Defects. VTS 2003: 385-392
82		Md. Saffat Quasem, Zhigang Jiang, Sandeep K. Gupta: Benefits of a SoC-Specific Test Methodology. IEEE Design & Test of Computers 20(3): 68-77 (2003)
	2002
81		Wichian Sirisaengtaksin, Sandeep K. Gupta: Enhanced Crosstalk Fault Model and Methodology to Generate Tests for Arbitrary Inter-core Interconnect Topology. Asian Test Symposium 2002: 163-169
80		I-De Huang, Sandeep K. Gupta, Melvin A. Breuer: Accurate and Efficient Static Timing Analysis with Crosstalk. ICCD 2002: 265-272
79		Shahin Nazarian, Hang Huang, Suriyaprakash Natarajan, Sandeep K. Gupta, Melvin A. Breuer: XIDEN: Crosstalk Target Identification Framework. ITC 2002: 365-374
78		Zhigang Jiang, Sandeep K. Gupta: An ATPG for Threshold Testing: Obtaining Acceptable Yield in Future Processes. ITC 2002: 824-833
77		Wei-Yu Chen, Sandeep K. Gupta, Melvin A. Breuer: Analytical models for crosstalk excitation and propagation in VLSI circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 21(10): 1117-1131 (2002)
76		Seongmoon Wang, Sandeep K. Gupta: DS-LFSR: a BIST TPG for low switching activity. IEEE Trans. on CAD of Integrated Circuits and Systems 21(7): 842-851 (2002)
75		Seongmoon Wang, Sandeep K. Gupta: An automatic test pattern generator for minimizing switching activity during scan testing activity. IEEE Trans. on CAD of Integrated Circuits and Systems 21(8): 954-968 (2002)
74		Wei-Yu Chen, Sandeep K. Gupta, Melvin A. Breuer: Test Generation for Crosstalk-Induced Faults: Framework and Computational Results. J. Electronic Testing 18(1): 17-28 (2002)
73		Liang-Chi Chen, Sandeep K. Gupta, Melvin A. Breuer: TA-PSV - Timing Analysis for Partially Specified Vectors. J. Electronic Testing 18(1): 73-88 (2002)
	2001
72		Liang-Chi Chen, Sandeep K. Gupta, Melvin A. Breuer: A New Gate Delay Model for Simultaneous Switching and Its Applications. DAC 2001: 289-294
71		Md. Saffat Quasem, Sandeep K. Gupta: Exact fault simulation for systems on Silicon that protects each core's intellectual property. DATE 2001: 804
70		Suriyaprakash Natarajan, Sandeep K. Gupta, Melvin A. Breuer: Switch-level delay test of domino logic circuits. ITC 2001: 367-376
69		Liang-Chi Chen, T. M. Mak, Sandeep K. Gupta, Melvin A. Breuer: Crosstalk test generation on pseudo industrial circuits: a case study. ITC 2001: 548-557
68		Sultan M. Al-Harbi, Sandeep K. Gupta: An Efficient Methodology for Generating Optimal and Uniform March Tests. VTS 2001: 231-239
67		Yi-Shing Chang, Sandeep K. Gupta, Melvin A. Breuer: Test Generation for Maximizing Ground Bounce for Internal Circuitry with Reconvergent Fan-out. VTS 2001: 358-367
66		Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer: Introducing redundant computations in RTL data paths for reducing BIST resources. ACM Trans. Design Autom. Electr. Syst. 6(3): 423-445 (2001)
65		Pankaj Pant, Yuan-Chieh Hsu, Sandeep K. Gupta, Abhijit Chatterjee: Path delay fault diagnosis in combinational circuits with implicitfault enumeration. IEEE Trans. on CAD of Integrated Circuits and Systems 20(10): 1226-1235 (2001)
	2000
64		Liang-Chi Chen, Sandeep K. Gupta, Melvin A. Breuer: A new framework for static timing analysis, incremental timing refinement, and timing simulation. Asian Test Symposium 2000: 102-107
63		Wei-Yu Chen, Sandeep K. Gupta, Melvin A. Breuer: Test generation for crosstalk-induced faults: framework and computational result. Asian Test Symposium 2000: 305-310
62		Chen-Huan Chiang, Sandeep K. Gupta: BIST TPG for SRAM cluster interconnect testing at board level. Asian Test Symposium 2000: 58-65
61		Sandeep K. Gupta, Wang-Chien Lee, Pradip K. Srimani: Message from the Chairs. ICPP Workshops 2000: 3
60		Nabil M. Abdulrazzaq, Sandeep K. Gupta: Test generation for path-delay faults in one-dimensional iterative logic arrays. ITC 2000: 326-335
59		Melvin A. Breuer, Sandeep K. Gupta: New Validation and Test Problems for High Performance Deep Submicron VLSI Circuits. VLSI Design 2000: 8
58		Hugo Cheung, Sandeep K. Gupta: A Framework to Minimize Test Escape and Yield Loss during IDDQ Testing: A Case Study. VTS 2000: 89-96
57		Rajagopalan Srinivasan, Sandeep K. Gupta, Melvin A. Breuer: Novel Test Pattern Generators for Pseudoexhaustive Testing. IEEE Trans. Computers 49(11): 1228-1240 (2000)
56		Chen-Huan Chiang, Sandeep K. Gupta: BIST TPG for Combinational Cluster Interconnect Testing at Board Level. J. Electronic Testing 16(5): 427-442 (2000)
	1999
55		Arani Sinha, Sandeep K. Gupta, Melvin A. Breuer: Validation and test generation for oscillatory noise in VLSI interconnects. ICCAD 1999: 289-296
54		Suriyaprakash Natarajan, Sandeep K. Gupta, Melvin A. Breuer: Switch-level delay test. ITC 1999: 171-180
53		Wei-Yu Chen, Sandeep K. Gupta, Melvin A. Breuer: Test generation for crosstalk-induced delay in integrated circuits. ITC 1999: 191-200
52		Seongmoon Wang, Sandeep K. Gupta: LT-RTPG: a new test-per-scan BIST TPG for low heat dissipation. ITC 1999: 85-94
51		Yi-Shing Chang, Sandeep K. Gupta, Melvin A. Breuer: Test Generation for Ground Bounce in Internal Logic Circuitry. VTS 1999: 95-105
	1998
50		Chen-Huan Chiang, Sandeep K. Gupta: BIST TPG for Combinational Cluster (Glue Logic) Interconnect Testing at Board Level. Asian Test Symposium 1998: 244-252
49		Yuan-Chieh Hsu, Sandeep K. Gupta: An Automatic Test Pattern Generator for At-Speed Robust Path Delay Testing. Asian Test Symposium 1998: 88-95
48		Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer: Introducing Redundant Computations in a Behavior for Reducing BIST Resources. DAC 1998: 548-553
47		Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer: Scheduling and Module Assignment for Reducing Bist Resources. DATE 1998: 66-73
46		Suriyaprakash Natarajan, Melvin A. Breuer, Sandeep K. Gupta: Process Variations and their Impact on Circuit Operation. DFT 1998: 73-
45		Weiyu Chen, Sandeep K. Gupta, Melvin A. Breuer: Test generation in VLSI circuits for crosstalk noise. ITC 1998: 641-650
44		Yuan-Chieh Hsu, Sandeep K. Gupta: A new path-oriented effect-cause methodology to diagnose delay failures. ITC 1998: 758-767
43		Sultan M. Al-Harbi, Sandeep K. Gupta: A Methodology for Transforming Memory Tests for In-System Testing of Direct Mapped Cache Tags. VTS 1998: 394-400
42		Seongmoon Wang, Sandeep K. Gupta: ATPG for Heat Dissipation Minimization During Test Application. IEEE Trans. Computers 47(2): 256-262 (1998)
41		Rajagopalan Srinivasan, Sandeep K. Gupta, Melvin A. Breuer: Bounds on pseudoexhaustive test lengths. IEEE Trans. VLSI Syst. 6(3): 420-431 (1998)
40		Chih-Ang Chen, Sandeep K. Gupta: Efficient BIST TPG design and test set compaction via input reduction. IEEE Trans. on CAD of Integrated Circuits and Systems 17(8): 692-705 (1998)
39		Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer: Allocation Techniques for Reducing BIST Area Overhead of Data Paths. J. Electronic Testing 13(2): 149-166 (1998)
38		Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer: Estimation of BIST Resources During High-Level Synthesis. J. Electronic Testing 13(3): 221-237 (1998)
	1997
37		Seongmoon Wang, Sandeep K. Gupta: ATPG for Heat Dissipation Minimization During Scan Testing. DAC 1997: 614-619
36		Chen-Huan Chiang, Sandeep K. Gupta: BIST TPG for faults in system backplanes. ICCAD 1997: 406-413
35		Weiyu Chen, Melvin A. Breuer, Sandeep K. Gupta: Analytic Models for Crosstalk Delay and Pulse Analysis Under Non-Ideal Inputs. ITC 1997: 809-818
34		Seongmoon Wang, Sandeep K. Gupta: DS-LFSR: A New BIST TPG for Low Heat Dissipation. ITC 1997: 848-857
33		Yi-Shing Chang, Sandeep K. Gupta, Melvin A. Breuer: Analysis of Ground Bounce in Deep Sub-Micron Circuits. VTS 1997: 110-116
32		Chen-Huan Chiang, Sandeep K. Gupta: BIST TPGs for Faults in Board Level Interconnect via Boundary Scan. VTS 1997: 376-383
31		Liang-Chi Chen, Sandeep K. Gupta, Melvin A. Breuer: High Quality Robust Tests for Path Delay Faults. VTS 1997: 88-93
	1996
30		Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer: Lower Bounds on Test Resources for Scheduled Data Flow Graphs. DAC 1996: 143-148
29		Chih-Ang Chen, Sandeep K. Gupta: A Satisfiability-Based Test Generator for Path Delay Faults in Combinational Circuts. DAC 1996: 209-214
28		Zhiyong Li, John H. Reif, Sandeep K. Gupta: Synthesizing Efficient Out-of-Core Programs for Block Recursive Algorithms Using Block-Cyclic Data Distributions. ICPP, Vol. 2 1996: 142-149
27		Hugo Cheung, Sandeep K. Gupta: A BIST Methodology for Comprehensive Testing of RAM with Reduced Heat Dissipation. ITC 1996: 386-395
26		Melvin A. Breuer, Sandeep K. Gupta: Process-Aggravated Noise (PAN): New Validation and Test Problems. ITC 1996: 914-923
25		Sandeep K. Gupta, Slawomir Pilarski, Sudhakar M. Reddy, Jacob Savir, Prab Varma: Delay Fault Testing: How Robust are Our Models? VTS 1996: 502-503
24		Sandeep K. Gupta, Dhiraj K. Pradhan: Utilization of On-Line (Concurrent) Checkers During Built-In-Self-Test and Vice Versa. IEEE Trans. Computers 45(1): 63-73 (1996)
23		Yuan-Chieh Hsu, Sandeep K. Gupta: A Simulator for At-Speed Robust Testing of Path Delay Faults in Combinational Circuits. IEEE Trans. Computers 45(11): 1312-1318 (1996)
22		Chih-Ang Chen, Sandeep K. Gupta: BIST Test Pattern Generators for Two-Pattern Testing-Theory and Design Algorithms. IEEE Trans. Computers 45(3): 257-269 (1996)
21		Chih-Ang Chen, Sandeep K. Gupta: Design of efficient BIST test pattern generators for delay testing. IEEE Trans. on CAD of Integrated Circuits and Systems 15(12): 1568-1575 (1996)
	1995
20		Sandeep K. Gupta, John D. Kececioglu, Alejandro A. Schäffer: Making the Shortest-Paths Approach to Sum-of-Pairs Multiple Sequence Alignment More Space Efficient in Practice (Extended Abstract). CPM 1995: 128-143
19		Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer: Data Path Allocation for Synthesizing RTL Designs with Low BIST Area Overhead. DAC 1995: 395-401
18		Chih-Ang Chen, Sandeep K. Gupta: A Methodology to Design Efficient BIST Test Pattern Generators. ITC 1995: 814-823
17		Mody Lempel, Sandeep K. Gupta: Zero Aliasing for Modeled Faults. IEEE Trans. Computers 44(11): 1283-1295 (1995)
16		Mody Lempel, Sandeep K. Gupta, Melvin A. Breuer: Test embedding with discrete logarithms. IEEE Trans. on CAD of Integrated Circuits and Systems 14(5): 554-566 (1995)
15		Sandeep K. Gupta, John D. Kececioglu, Alejandro A. Schäffer: Improving the Practical Space and Time Efficiency of the Shortest-Paths Approach to Sum-of-Pairs Multiple Sequence Alignment. Journal of Computational Biology 2(3): 459-472 (1995)
	1994
14		Wen-Chang Fang, Sandeep K. Gupta: Clock Grouping: A Low Cost DFT Methodology for Delay Testing. DAC 1994: 94-99
13		Sen-Pin Lin, Sandeep K. Gupta, Melvin A. Breuer: A Low Cost BIST Methodology and Associated Novel Test Pattern Generator. EDAC-ETC-EUROASIC 1994: 106-112
12		Chih-Ang Chen, Sandeep K. Gupta: BIST Test Pattern Generators for Stuck-Open and Delay Testing. EDAC-ETC-EUROASIC 1994: 289-296
11		Chen-Huan Chiang, Sandeep K. Gupta: Random pattern testable logic synthesis. ICCAD 1994: 125-128
10		Seongmoon Wang, Sandeep K. Gupta: ATPG for Heat Dissipation Minimization During Test Application. ITC 1994: 250-258
	1993
9		Rajagopalan Srinivasan, Sandeep K. Gupta, Melvin A. Breuer: An Efficient Partitioning Strategy for Pseudo-Exhaustive Testing. DAC 1993: 242-248
8		Rajagopalan Srinivasan, Sandeep K. Gupta, Melvin A. Breuer: Novel Test Pattern Generators for Pseudo-Exhaustive Testing. ITC 1993: 1041-1050
	1992
7		Sandeep K. Gupta, Dhiraj K. Pradhan: Can Concurrent Checkers Help BIST? ITC 1992: 140-150
	1991
6		Mark G. Karpovsky, Sandeep K. Gupta, Dhiraj K. Pradhan: Aliasing and Diagnosis Probability in MISR and STUMPS Using a General Error Model. ITC 1991: 828-839
5		Dhiraj K. Pradhan, Sandeep K. Gupta: A New Framework for Designing and Analyzing BIST Techniques and Zero Aliasing Compression. IEEE Trans. Computers 40(6): 743-763 (1991)
	1990
4		Sandeep K. Gupta, Dhiraj K. Pradhan, Sudhakar M. Reddy: Zero aliasing compression. FTCS 1990: 254-263
3		Dhiraj K. Pradhan, Sandeep K. Gupta, Mark G. Karpovsky: Aliasing Probability for Multiple Input Signature Analyzer. IEEE Trans. Computers 39(4): 586-591 (1990)
	1988
2		Sandeep K. Gupta, Dhiraj K. Pradhan: A New Framework for Designing and Analyzing BIST Techniques: Computation of Exact Aliasing Probability. ITC 1988: 329-342
1		Sandeep K. Gupta, Melvin A. Breuer, Jung-Cheun Lien: Concurrent Control of Multiple BIT Structures. ITC 1988: 431-442

Coauthor Index

1	Nabil M. Abdulrazzaq	[60] [85]
2	Sultan M. Al-Harbi	[43] [68] [84]
3	Murali Annavaram	[115]
4	Melvin A. Breuer	[1] [8] [9] [13] [16] [19] [26] [30] [31] [33] [35] [38] [39] [41] [45] [46] [47] [48] [51] [53] [54] [55] [57] [59] [63] [64] [66] [67] [69] [70] [72] [73] [74] [77] [79] [80] [83] [86] [90] [91] [93] [94] [96] [97] [104] [115] [116] [119] [120] [124]
5	Byeongju Cha	[125]
6	Jae Chul Cha	[110] [111] [112] [123]
7	Sreejit Chakravarty	[108]
8	Yi-Shing Chang	[33] [51] [67] [86] [108] [109]
9	Abhijit Chatterjee	[65]
10	Chih-Ang Chen	[12] [18] [21] [22] [29] [40]
11	Liang-Chi Chen	[31] [64] [69] [72] [73]
12	Wei-Yu Chen	[53] [63] [74] [77]
13	Weiyu Chen	[35] [45]
14	Hugo Cheung	[27] [58] [106]
15	Chen-Huan Chiang	[11] [32] [36] [50] [56] [62]
16	Kun Young Chung	[87] [102] [114] [117]
17	Prasanjeet Das	[122]
18	Wen-Chang Fang	[14]
19	Jean-Luc Gaudiot	[107]
20	Tong-Yu Hsieh	[115]
21	Yuan-Chieh Hsu	[23] [44] [49] [65]
22	Hsunwei Hsuing	[125]
23	Hang Huang	[79]
24	I-De Huang	[80] [99] [108] [109]
25	Shahdad Irajpour	[83] [93] [97]
26	Zhigang Jiang	[78] [82] [89] [98] [113]
27	Jung-Yup Kang	[107]
28	Mark G. Karpovsky	[3] [6]
29	John D. Kececioglu	[15] [20]
30	Kuen-Jong Lee	[115]
31	Wang-Chien Lee	[61]
32	Mody Lempel	[16] [17]
33	Zhiyong Li	[28]
34	Jung-Cheun Lien	[1]
35	Sen-Pin Lin	[13]
36	T. M. Mak	[69] [91]
37	Mohammad Mirza-Aghatabar	[116] [119] [120] [124]
38	Suriyaprakash Natarajan	[46] [54] [70] [79] [109]
39	Shahin Nazarian	[79] [83] [96] [104] [124]
40	Pankaj Pant	[65]
41	Ishwar Parulkar	[19] [30] [38] [39] [47] [48] [66]
42	Massoud Pedram	[104]
43	Slawomir Pilarski	[25]
44	Dhiraj K. Pradhan	[2] [3] [4] [5] [6] [7] [24]
45	Md. Saffat Quasem	[71] [82] [88] [92]
46	Sudhakar M. Reddy	[4] [25]
47	John H. Reif	[28]
48	Jacob Savir	[25]
49	Alejandro A. Schäffer	[15] [20]
50	Shideh Shahidi	[103] [105]
51	Ramesh Sharma	[109]
52	Doochul Shin	[118] [121]
53	Arani Sinha	[55] [90]
54	Wichian Sirisaengtaksin	[81] [95] [100]
55	Pradip K. Srimani	[61]
56	Rajagopalan Srinivasan	[8] [9] [41] [57]
57	Prab Varma	[25]
58	Lei Wang	[83] [94]
59	Seongmoon Wang	[10] [34] [37] [42] [52] [75] [76] [101]

Colors in the list of coauthors

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