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| 2012 | ||
|---|---|---|
| 62 | Luis Angel D. Bathen, Nikil D. Dutt, Alex Nicolau, Puneet Gupta: VaMV: Variability-aware Memory Virtualization. DATE 2012: 284-287 | |
| 61 | Tuck-Boon Chan, Puneet Gupta, Andrew B. Kahng, Liangzhen Lai: DDRO: A novel performance monitoring methodology based on design-dependent ring oscillators. ISQED 2012: 633-640 | |
| 60 | John Lee, Puneet Gupta: Discrete Circuit Optimization: Library Based Gate Sizing and Threshold Voltage Assignment. Foundations and Trends in Electronic Design Automation 6(1): 1-120 (2012) | |
| 59 | Abde Ali Kagalwalla, Puneet Gupta, Christopher J. Progler, Steve McDonald: Design-Aware Mask Inspection. IEEE Trans. on CAD of Integrated Circuits and Systems 31(5): 690-702 (2012) | |
| 2011 | ||
| 58 | Puneet Gupta, Rajesh K. Gupta: Underdesigned and Opportunistic Computing. Asian Test Symposium 2011: 498-499 | |
| 57 | Lucas Wanner, Rahul Balani, Sadaf Zahedi, Charwak Apte, Puneet Gupta, Mani B. Srivastava: Variability-aware duty cycle scheduling in long running embedded sensing systems. DATE 2011: 131-136 | |
| 56 | Tuck-Boon Chan, John Sartori, Puneet Gupta, Rakesh Kumar: On the efficacy of NBTI mitigation techniques. DATE 2011: 932-937 | |
| 55 | Rani S. Ghaida, Kanak B. Agarwal, Sani R. Nassif, Xin Yuan, Lars Liebmann, Puneet Gupta: A framework for double patterning-enabled design. ICCAD 2011: 14-20 | |
| 54 | Puneet Gupta, Scott D. Stoller, Zhongyuan Xu: Abductive Analysis of Administrative Policies in Rule-Based Access Control. ICISS 2011: 116-130 | |
| 53 | Parag Kulkarni, Puneet Gupta, Milos D. Ercegovac: Trading Accuracy for Power with an Underdesigned Multiplier Architecture. VLSI Design 2011: 346-351 | |
| 52 | Lerong Cheng, Puneet Gupta, Costas J. Spanos, Kun Qian, Lei He: Physically Justifiable Die-Level Modeling of Spatial Variation in View of Systematic Across Wafer Variability. IEEE Trans. on CAD of Integrated Circuits and Systems 30(3): 388-401 (2011) | |
| 51 | Parag Kulkarni, Puneet Gupta, Milos D. Ercegovac: Trading Accuracy for Power in a Multiplier Architecture. J. Low Power Electronics 7(4): 490-501 (2011) | |
| 2010 | ||
| 50 | Aashish Pant, Puneet Gupta, Mihaela van der Schaar: Software adaptation in quality sensitive applications to deal with hardware variability. ACM Great Lakes Symposium on VLSI 2010: 85-90 | |
| 49 | Lerong Cheng, Puneet Gupta, Lei He: On confidence in characterization and application of variation models. ASP-DAC 2010: 751-756 | |
| 48 | Puneet Gupta, Andrew B. Kahng, Amarnath Kasibhatla, Puneet Sharma: Eyecharts: constructive benchmarking of gate sizing heuristics. DAC 2010: 597-602 | |
| 47 | Tuck-Boon Chan, Aashish Pant, Lerong Cheng, Puneet Gupta: Design dependent process monitoring for back-end manufacturing cost reduction. ICCAD 2010: 116-122 | |
| 46 | Abde Ali Kagalwalla, Puneet Gupta, Christopher J. Progler, Steve McDonald: Design-aware mask inspection. ICCAD 2010: 93-99 | |
| 45 | John Lee, Puneet Gupta: Incremental gate sizing for late process changes. ICCD 2010: 215-221 | |
| 44 | John Sartori, Aashish Pant, Rakesh Kumar, Puneet Gupta: Variation-aware speed binning of multi-core processors. ISQED 2010: 307-314 | |
| 43 | Tuck-Boon Chan, Puneet Gupta: On Electrical Modeling of Imperfect Diffusion Patterning. VLSI Design 2010: 224-229 | |
| 42 | Tuck-Boon Chan, Rani S. Ghaida, Puneet Gupta: Electrical Modeling of Lithographic Imperfections. VLSI Design 2010: 423-428 | |
| 41 | Jason Cong, Puneet Gupta, John Lee: Evaluating Statistical Power Optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 29(11): 1750-1762 (2010) | |
| 2009 | ||
| 40 | Weihuan Shu, Kumar Padmanabh, Puneet Gupta: Prioritized Buffer Management Policy for Wireless Sensor Nodes. AINA Workshops 2009: 787-792 | |
| 39 | Jason Cong, Puneet Gupta, John Lee: On the futility of statistical power optimization. ASP-DAC 2009: 167-172 | |
| 38 | Lerong Cheng, Puneet Gupta, Lei He: Accounting for non-linear dependence using function driven component analysis. ASP-DAC 2009: 474-479 | |
| 37 | Lerong Cheng, Puneet Gupta, Costas J. Spanos, Kun Qian, Lei He: Physically justifiable die-level modeling of spatial variation in view of systematic across wafer variability. DAC 2009: 104-109 | |
| 36 | Rani S. Ghaida, Puneet Gupta: A framework for early and systematic evaluation of design rules. ICCAD 2009: 615-622 | |
| 35 | Puneet Gupta, Scott D. Stoller: Verification of Security Policy Enforcement in Enterprise Systems. SEC 2009: 202-213 | |
| 34 | Lerong Cheng, Puneet Gupta, Lei He: Efficient Additive Statistical Leakage Estimation. IEEE Trans. on CAD of Integrated Circuits and Systems 28(11): 1777-1781 (2009) | |
| 2008 | ||
| 33 | Puneet Gupta, Andrew B. Kahng, Youngmin Kim, Saumil Shah, Dennis Sylvester: Investigation of diffusion rounding for post-lithography analysis. ASP-DAC 2008: 480-485 | |
| 32 | Kartik Muralidharan, G. V. Karthik, Puneet Gupta, Atanu Roy Chowdhury: mConnect: A context aware mobile transaction middleware. COMSWARE 2008: 381-386 | |
| 31 | Mohit Saxena, Puneet Gupta, Bijendra N. Jain: Experimental analysis of RSSI-based location estimation in wireless sensor networks. COMSWARE 2008: 503-510 | |
| 30 | Puneet Gupta, Andrew B. Kahng: Bounded-lifetime integrated circuits. DAC 2008: 347-348 | |
| 29 | Dan Bailey, Eric Soenen, Puneet Gupta, Paul G. Villarrubia, Sang H. Dhong: Challenges at 45nm and beyond. ICCAD 2008: 7 | |
| 2007 | ||
| 28 | Puneet Gupta, Andrew B. Kahng, Youngmin Kim, Saumil Shah, Dennis Sylvester: Line-End Shortening is Not Always a Failure. DAC 2007: 270-271 | |
| 27 | Puneet Gupta, Andrew B. Kahng, Chul-Hong Park: Detailed Placement for Enhanced Control of Resist and Etch CDs. IEEE Trans. on CAD of Integrated Circuits and Systems 26(12): 2144-2157 (2007) | |
| 26 | Puneet Gupta, Andrew B. Kahng, Youngmin Kim, Dennis Sylvester: Self-Compensating Design for Reduction of Timing and Leakage Sensitivity to Systematic Pattern-Dependent Variation. IEEE Trans. on CAD of Integrated Circuits and Systems 26(9): 1614-1624 (2007) | |
| 2006 | ||
| 25 | Saumil Shah, Puneet Gupta, Andrew B. Kahng: Standard cell library optimization for leakage reduction. DAC 2006: 983-986 | |
| 24 | Puneet Gupta, Andrew B. Kahng: Efficient Design and Analysis of Robust Power Distribution Meshes. VLSI Design 2006: 337-342 | |
| 23 | Puneet Gupta, Andrew B. Kahng, Chul-Hong Park, Kambiz Samadi, Xu Xu: Wafer Topography-Aware Optical Proximity Correction. IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2747-2756 (2006) | |
| 22 | Puneet Gupta, Andrew B. Kahng, Puneet Sharma, Dennis Sylvester: Gate-length biasing for runtime-leakage control. IEEE Trans. on CAD of Integrated Circuits and Systems 25(8): 1475-1485 (2006) | |
| 2005 | ||
| 21 | Puneet Gupta, Andrew B. Kahng, Chul-Hong Park: Detailed placement for improved depth of focus and CD control. ASP-DAC 2005: 343-348 | |
| 20 | Puneet Gupta, Andrew B. Kahng, Youngmin Kim, Dennis Sylvester: Advanced Timing Analysis Based on Post-OPC Extraction of Critical Dimensions. DAC 2005: 365-368 | |
| 19 | Puneet Gupta, Andrew B. Kahng, Dennis Sylvester, Jie Yang: Performance Driven OPC for Mask Cost Reduction. ISQED 2005: 270-275 | |
| 18 | Puneet Gupta, Andrew B. Kahng, Puneet Sharma: A Practical Transistor-Level Dual Threshold Voltage Assignment Methodology. ISQED 2005: 421-426 | |
| 17 | Puneet Gupta, Andrew B. Kahng, Stefanus Mantik: Routing-aware scan chain ordering. ACM Trans. Design Autom. Electr. Syst. 10(3): 546-560 (2005) | |
| 16 | Puneet Gupta, Andrew B. Kahng, Ion I. Mandoiu, Puneet Sharma: Layout-aware scan chain synthesis for improved path delay fault coverage. IEEE Trans. on CAD of Integrated Circuits and Systems 24(7): 1104-1114 (2005) | |
| 2004 | ||
| 15 | Luigi Capodieci, Puneet Gupta, Andrew B. Kahng, Dennis Sylvester, Jie Yang: Toward a methodology for manufacturability-driven design rule exploration. DAC 2004: 311-316 | |
| 14 | Puneet Gupta, Fook-Luen Heng: Toward a systematic-variation aware timing methodology. DAC 2004: 321-326 | |
| 13 | Puneet Gupta, Andrew B. Kahng, Puneet Sharma, Dennis Sylvester: Selective gate-length biasing for cost-effective runtime leakage control. DAC 2004: 327-330 | |
| 12 | Puneet Gupta, Michael S. Hsiao: ALAPTF: A new Transition Faultmodel and the ATPG Algorithm. ITC 2004: 1053-1060 | |
| 11 | Puneet Gupta, Andrew B. Kahng, Youngmin Kim, Dennis Sylvester: Investigation of performance metrics for interconnect stack architectures. SLIP 2004: 23-29 | |
| 10 | Puneet Gupta, Andrew B. Kahng: Wire Swizzling to Reduce Delay Uncertainty Due to Capacitive Coupling. VLSI Design 2004: 431-436 | |
| 9 | Puneet Gupta, Deependra Moitra: Evolving a pervasive IT infrastructure: a technology integration approach. Personal and Ubiquitous Computing 8(1): 31-41 (2004) | |
| 2003 | ||
| 8 | Puneet Gupta, Andrew B. Kahng, Dennis Sylvester, Jie Yang: A cost-driven lithographic correction methodology based on off-the-shelf sizing tools. DAC 2003: 16-21 | |
| 7 | Yu Chen, Puneet Gupta, Andrew B. Kahng: Performance-impact limited area fill synthesis. DAC 2003: 22-27 | |
| 6 | Puneet Gupta, Andrew B. Kahng: Manufacturing-Aware Physical Design. ICCAD 2003: 681-688 | |
| 5 | Puneet Gupta, Andrew B. Kahng, Ion I. Mandoiu, Puneet Sharma: Layout-Aware Scan Chain Synthesis for Improved Path Delay Fault Coverage. ICCAD 2003: 754-759 | |
| 4 | Puneet Gupta, Andrew B. Kahng: Quantifying Error in Dynamic Power Estimation of CMOS Circuits. ISQED 2003: 273-278 | |
| 3 | Puneet Gupta, Andrew B. Kahng, Stefanus Mantik: A Proposal for Routing-Based Timing-Driven Scan Chain Ordering. ISQED 2003: 339-343 | |
| 2 | Puneet Gupta, Michael S. Hsiao: High Quality ATPG for Delay Defects. ITC 2003: 584-591 | |
| 2002 | ||
| 1 | Puneet Gupta, David S. Doermann, Daniel DeMenthon: Beam Search for Feature Selection in Automatic SVM Defect Classification. ICPR (2) 2002: 212-215 | |
Colors in the list of coauthors
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