Pallav Gupta

	2012
15		Naghmeh Karimi, Krishnendu Chakrabarty, Pallav Gupta, Srinivas Patil: Test generation for clock-domain crossing faults in integrated circuits. DATE 2012: 406-411
	2011
14		Naghmeh Karimi, Zhiqiu Kong, Krishnendu Chakrabarty, Pallav Gupta, Srinivas Patil: Testing of Clock-Domain Crossing Faults in Multi-core System-on-Chip. Asian Test Symposium 2011: 7-14
13		Xiaofang Wang, Pallav Gupta: Resource-constrained multiprocessor synthesis for floating-point applications on FPGAs. ACM Trans. Design Autom. Electr. Syst. 16(4): 41 (2011)
	2008
12		Pallav Gupta, Rui Zhang, Niraj K. Jha: Automatic Test Generation for Combinational Threshold Logic Networks. IEEE Trans. VLSI Syst. 16(8): 1035-1045 (2008)
	2007
11		Pallav Gupta, Niraj K. Jha, Loganathan Lingappan: A Test Generation Framework for Quantum Cellular Automata Circuits. IEEE Trans. VLSI Syst. 15(1): 24-36 (2007)
10		Rui Zhang, Pallav Gupta, Niraj K. Jha: Majority and Minority Network Synthesis With Application to QCA-, SET-, and TPL-Based Nanotechnologies. IEEE Trans. on CAD of Integrated Circuits and Systems 26(7): 1233-1245 (2007)
	2006
9		Pallav Gupta, Niraj K. Jha, Loganathan Lingappan: Test generation for combinational quantum cellular automata (QCA) circuits. DATE 2006: 311-316
8		Pallav Gupta, Abhinav Agrawal, Niraj K. Jha: An Algorithm for Synthesis of Reversible Logic Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 25(11): 2317-2330 (2006)
	2005
7		Pallav Gupta, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha: Efficient fingerprint-based user authentication for embedded systems. DAC 2005: 244-247
6		Rui Zhang, Pallav Gupta, Niraj K. Jha: Synthesis of Majority and Minority Networks and Its Applications to QCA, TPL and SET Based Nanotechnologies. VLSI Design 2005: 229-234
5		Rui Zhang, Pallav Gupta, Lin Zhong, Niraj K. Jha: Threshold network synthesis and optimization and its application to nanotechnologies. IEEE Trans. on CAD of Integrated Circuits and Systems 24(1): 107-118 (2005)
	2004
4		Rui Zhang, Pallav Gupta, Lin Zhong, Niraj K. Jha: Synthesis and Optimization of Threshold Logic Networks with Application to Nanotechnologies. DATE 2004: 904-909
3		Pallav Gupta, Niraj K. Jha: An Algorithm for Nano-Pipelining of Circuits and Architectures for a Nanotechnology. DATE 2004: 974-979
2		Pallav Gupta, Rui Zhang, Niraj K. Jha: An Automatic Test Pattern Generation Framework for Combinational Threshold Logic Networks. ICCD 2004: 540-543
	2003
1		Pallav Gupta, Lin Zhong, Niraj K. Jha: A High-level Interconnect Power Model for Design Space Exploration. ICCAD 2003: 551-559

Coauthor Index

1	Abhinav Agrawal	[8]
2	Krishnendu Chakrabarty	[14] [15]
3	Niraj K. Jha	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
4	Naghmeh Karimi	[14] [15]
5	Zhiqiu Kong	[14]
6	Loganathan Lingappan	[9] [11]
7	Srinivas Patil	[14] [15]
8	Anand Raghunathan	[7]
9	Srivaths Ravi	[7]
10	Xiaofang Wang	[13]
11	Rui Zhang	[2] [4] [5] [6] [10] [12]
12	Lin Zhong	[1] [4] [5]

Colors in the list of coauthors

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