Avaneendra Gupta

	2000
6		Avaneendra Gupta, John P. Hayes: CLIP: integer-programming-based optimal layout synthesis of 2D CMOS cells. ACM Trans. Design Autom. Electr. Syst. 5(3): 510-547 (2000)
	1999
5		Avaneendra Gupta, John P. Hayes: Near-Optimum Hierarchical Layout Synthesis of Two-Dimensional CMOS Cells. VLSI Design 1999: 453-459
	1998
4		Avaneendra Gupta, John P. Hayes: Optimal 2-D cell layout with integrated transistor folding. ICCAD 1998: 128-135
	1997
3		Avaneendra Gupta, John P. Hayes: CLIP: An Optimizing Layout Generator for Two-Dimensional CMOS Cells. DAC 1997: 452-455
2		Avaneendra Gupta, John P. Hayes: A Hierarchical Technique for Minimum-Width Layout of Two-Dimensional CMOS Cells. VLSI Design 1997: 15-20
	1996
1		Avaneendra Gupta, John P. Hayes: Width minimization of two-dimensional CMOS cells using integer programming. ICCAD 1996: 660-667

Coauthor Index

1

John P. Hayes

[1] [2] [3] [4] [5] [6]

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