Jonhson Guo

	2005
1		Laung-Terng Wang, Xiaoqing Wen, Po-Ching Hsu, Shianling Wu, Jonhson Guo: At-Speed Logic BIST Architecture for Multi-Clock Designs. ICCD 2005: 475-478

Coauthor Index

1	Po-Ching Hsu	[1]
2	Laung-Terng Wang	[1]
3	Xiaoqing Wen	[1]
4	Shianling Wu	[1]

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