 | 2011 |
|---|
| 7 |       | Erbao Li,
Kiran K. Gunnam,
David Declercq:
Trellis based Extended Min-Sum for decoding nonbinary LDPC codes.
ISWCS 2011: 46-50 |
| 2009 |
|---|
| 6 | | Weihuang Wang,
Gwan S. Choi,
Kiran K. Gunnam:
Low-Power VLSI Design of LDPC Decoder Using DVFS for AWGN Channels.
VLSI Design 2009: 51-56 |
| 5 | | Kiran K. Gunnam,
Gwan S. Choi,
Mark B. Yeary:
Comments on "Techniques and Architectures for Hazard-Free Semi-Parallel Decoding of LDPC Codes".
EURASIP J. Emb. Sys. 2009: (2009) |
| 4 | | Weihuang Wang,
Euncheol Kim,
Kiran K. Gunnam,
Gwan S. Choi:
Low-Power VLSI Design of LDPC Decoder Using Dynamic Voltage and Frequency Scaling for Additive White Gaussian Noise Channels.
J. Low Power Electronics 5(3): 303-312 (2009) |
| 2007 |
|---|
| 3 | | Kiran K. Gunnam,
Gwan S. Choi,
Mark B. Yeary,
Mohammed Atiquzzaman:
VLSI Architectures for Layered Decoding for Irregular LDPC Codes of WiMax.
ICC 2007: 4542-4547 |
| 2 | | Kiran K. Gunnam,
Gwan Choi,
Weihuang Wang,
Mark B. Yeary:
Multi-Rate Layered Decoder Architecture for Block LDPC Codes of the IEEE 802.11n Wireless Standard.
ISCAS 2007: 1645-1648 |
| 1 | | Kiran K. Gunnam,
Gwan S. Choi,
Mark B. Yeary:
A Parallel VLSI Architecture for Layered Decoding for Array LDPC Codes.
VLSI Design 2007: 738-743 |
Data released under the ODC-BY 1.0 license — See also our legal information page